ARM VERSION 1.2 manual Floating-point registers, Register banks

Vector Floating-point Programming

6.2Floating-point registers

The Vector Floating-point coprocessor has 32 single-precision registers, s0 to s31. Each register can contain either a single-precision floating-point value, or a 32-bit integer.

These 32 registers are also treated as 16 double-precision registers, d0 to d15. dn occupies the same hardware as s(2n) and s(2n+1).

You can use:

•some registers for single-precision values at the same time as you are using others for double-precision values

•the same registers for single-precision values and double-precision values at different times.

Do not attempt to use corresponding single-precision and double-precision registers at the same time. No damage is caused but the results are meaningless.

6.2.1Register banks

The VFP registers are arranged as four banks of:

•eight single-precision registers, s0 to s7, s8 to s15, s16 to s23, and s24 to s31

•four double-precision registers, d0 to d3, d4 to d7, d8 to d11, and d12 to d15

•any combination of single-precision and double-precision registers.

See Figure 6-1 for further clarification.

s0 s1 s2 s3 s4 s5 s6 s7 s8 ... s15 s16 ... s23 s24 ... s31

d0	d1	d2	d3	d4
	Bank 0

...

Bank 1

d7 d8

...

Bank 2

d11 d12

...

Bank 3

d15

Figure 6-1 VFP register banks

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