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ARM VERSION 1.2 Non word-aligned addresses, Loading or storing the base register, with writeback

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ARM Instruction Reference

Non word-aligned addresses

These instructions ignore bits [1:0] of the address. (On a system with a system coprocessor, if alignment checking is enabled, nonzero values in these bits cause an alignment exception.)

Loading to r15

A load to r15 (the program counter) causes a branch to the instruction at the address loaded. In T variants of ARM architecture v5 and above, a load to r15 causes a change to executing Thumb instructions if bit 0 of the value loaded is set.

Loading or storing the base register, with writeback

If Rn is in reglist, and writeback is specified with the ! suffix:

•if op is STM and Rn is the lowest-numbered register in reglist, the initial value of Rn is stored

•otherwise, the loaded or stored value of Rn is unpredictable.

Architectures

These instructions are available in all versions of the ARM architecture.

In T variants of ARM architecture v5 and above, a load to r15 causes a change to executing Thumb instructions if bit 0 of the value loaded is set.

Examples

LDMIA	r8,{r0,r2,r9}
STMDB	r1!,{r3-r6,r11,r12}
STMFD	r13!,{r0,r4-r7,LR}	; Push registers including the
		; stack pointer
LDMFD	r13!,{r0,r4-r7,PC}	; Pop the same registers and
		; return from subroutine

Incorrect examples

STMIA	r5!,{r5,r4,r9}	;	value stored for	r5 unpredictable
LDMDA	r2, {}	;	must be at least	one register in list

ARM DUI 0068B

Copyright © 2000, 2001 ARM Limited. All rights reserved.

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ARM VERSION 1.2 manual Non word-aligned addresses, Loading or storing the base register, with writeback

Contents

ARM Developer Suite ARM Developer Suite Assembler GuideCopyright 2000, 2001 ARM Limited. All rights reserved ARM Developer Suite Assembler Guide Glossary Feedback on About this book onAbout this book Using this bookIntended audience This book is organized into the following chaptersItalic Typographical conventionsFurther reading ARM publicationsOther publications ARM Reference Peripheral Specification ARM DDIFeedback Feedback on the ARM Developer SuiteFeedback on this book ARM DUI 0068B About the ARM Developer Suite assemblers on IntroductionARM Developer Suite ADS has About the ARM Developer Suite assemblersWriting ARM and Thumb Assembly Language Introduction Code examplesOr run the module in AXD with interleaving on See Architecture versions Overview of the ARM architectureARM and Thumb state ARM processors always start executing code in ARM stateProcessor mode RegistersGeneral-purpose, 32-bit registers Program counter pc ARM instruction set overview Branch instructionsData processing instructions Single register load and store instructions Status register access instructionsMultiple register load and store instructions Semaphore instructionsAccess to the inline barrel shifter Register accessARM instruction capabilities Following general points apply to ARM instructionsThumb instruction set overview Thumb instruction capabilitiesFollowing general points apply to Thumb instructions Differences between Thumb and ARM instruction sets Access to the barrel shifterSingle register load and store instructions Layout of assembly language source files Structure of assembly language modulesGeneral form of source lines in assembly language is Case rulesLabels Local labelsComments Is a base between 2 Xxx is a number in that base ConstantsELF sections and the Area directive An example ARM assembly language moduleApplication execution Entry directiveApplication termination END directiveCalling subroutines An example Thumb assembly language module CODE32 and CODE16 directivesBX instruction Example 2-4 Preprocessing an assembly language source file Using the C preprocessorALU status flags Conditional executionExamples Execution conditionsExample of the use of conditional execution Using conditional execution in ARM stateConditional branches only Branch prediction and caches Converting to ThumbLoading constants into registers Right, 2 bits Direct loading with MOV and MVNLoading with LDR Rd, =const Direct loading with MOV in Thumb statePlacing literal pools Loading floating-point constants Direct loading with ADR and Adrl Loading addresses into registersADR Implementing a jump table with ADR Example 2-7 ARM code jump table Example 2-8 Thumb code jump table Loading addresses with LDR Rd, = label R1, =Darea + = LDR R1,PC, #offset into Literal Pool An LDR Rd, =label example string copying Address registers. For example, the instructionIncrements r1 by Load register Load and store multiple register instructions Syntax ARM LDM and STM instructionsSyntax of the LDM instructions is WhereLDM and STM addressing modes UsageDescending or ascending Implementing stacks with LDM and STMStacking registers for nested subroutines Example 2-11 Block copy Block copy with LDM and STMMovs LDM and STM Thumb LDM and STM instructionsPush and POP Thumb-state block copy exampleLSR Test-and-branch macro example Using macrosThis macro can be invoked as follows After substitution this becomesRegister that holds the divisor Unsigned integer division macro exampleAfter the instructions are executed, it holds the remainder If only the remainder is requiredRatio DivMod r0,r5,r4,r2 Describing data structures with MAP and Field directives Relative maps Register-based maps Program-relative maps Finding the end of the allocated data Forcing correct alignment EndOfChars Defining register-based symbols Using register-based MAP and Field directivesIs equivalent to the C code Setting up a C-type structureMaking faster access possible If you want the equivalent of the C code2-27 for an explanation of these Not This example, the MAP directive isField MAP Using two register-based structures Avoiding problems with MAP and Field directives ArrayBase RN r9 Using frame directives Expressions, literals, and operators on Symbols onCommand syntax Position-independent. The default is /noropi Specifies that the content of inputfile is read-onlySpecifies that the content of inputfile is read-write Position-independent. The default is /norwpiSelection of libraries, accordingly Assembled for the wrong target FPUValid options are Selects no floating-point option. This makes your assembledSets the maximum source cache size to n. The default is 8MB Command-line optionsObject file, for use by the debugger see Keep on Allow unaligned LDRsAs \n and \t First pass and reads them from memory on the second passRegister names Turns off warning messagesAssembler Reference Format of source lines Predeclared register names Predefined register and coprocessor namesPredeclared program status register names Predeclared floating-point register namesBuilt-in variables Lists the built-in variables defined by the ARM assemblerExpressions or conditions, for example Determining the armasm version at assembly time Symbol naming rules SymbolsNumeric constants on Labels onNumeric constants VariablesGbls Assembly time substitution of variablesDCD and Dcdu on Dcfd and Dcfdu on Dcfs and Dcfsu on Program-relative labelsDCQ and Dcqu on DCW and Dcwu on Register-relative labelsSyntax of a reference to a local label is Syntax of a local label isAssembler Reference This section contains the following subsections Expressions, literals, and operatorsString literals String expressionsExample String literalsNumeric expressions Numeric literals Is a sequence of characters using only the digits 0 to nNumeric literals can take any of the following forms Numeric code of the characterFloating-point literals can take any of the following forms Floating-point literalsLogical expressions Register-relative and program-relative expressionsLogical literals There are only two logical literalsString manipulation Operator precedenceOperator precedence in C Precedence Operator Usage Description Unary operatorsExample of use of SBOFFSET1912 and SBOFFSET11 Binary operators Multiplicative operatorsString manipulation operators Shift operators SHR is a logical shift and does not propagate the sign bitAddition, subtraction, and logical operators Relational operators 10 shows the Boolean operators Boolean operatorsARM DUI 0068B ARM Instruction Reference Add with carry, Add All Logical Branch Move not All ARM condition codes Q flag LDR and STR, words and unsigned bytes on ARM memory access instructionsLDR and STR, halfwords and signed bytes on LDR and STR, doublewords onWhere Is either LDR Load Register or STR Store Register LDR and STR, words and unsigned bytesOtherwise, a 32-bit word is transferred Pre-indexed offset Zero offsetProgram-relative Post-indexed offsetFlexible offset syntax Loading to r15 Address alignment for word transfersArchitectures Saving from r15LDR and STR, halfwords and signed bytes Is an offset applied to the value in Rn see Offset syntax Must be within ±255 bytes of the current instructionOffset syntax Is often a numeric constant see examples belowAddress alignment for halfword transfers Offset syntax is the same for LDR and STR, doublewords onYou cannot load halfwords or bytes to r15 Incorrect exampleIs an optional condition code see Conditional execution on LDR and STR, doublewordsMust be an even numbered register, and not r14 Pre-indexed without writebackAddress alignment Not be the same as Rd or Rd+1Incorrect examples Is any one of the following Is either LDM or STMIncrement address after each transfer Increment address before each transferLoading or storing the base register, with writeback Non word-aligned addressesIs the register on which the memory address is based 5 PLDAlignment Is swapped with the contents of the memory location 6 SWPBoth Rd and Rm ARM general data processing instructions Flexible second operand Bits of the register are set to LSR and LSLInstruction substitution Carry flagIs one of ADD, SUB, RSB, ADC, SBC, or RSC 2 ADD, SUB, RSB, ADC, SBC, and RSCIs the ARM register for the result Is the ARM register holding the first operandCondition flags Use of r15Multiword arithmetic examples These instructions subtract one 96-bit integer from another 3 AND, ORR, EOR, and BIC Logical AND, OR, Exclusive or and Bit ClearIs one of AND, ORR, EOR, or BIC Orreq MOV and MVN Move and Move NotIs the ARM register for the result Mvnne Compare and Compare Negative CMP and CMNCMN Test and Test Equivalence TST and TEQTEQ Count Leading Zeroes 7 CLZIs the ARM register for the result. Rd must not be r15 Is the operand registerARM multiply instructions MUL and MLA onUMULL, UMLAL, Smull and Smlal on MUL and MLA MUL Is one of UMULL, UMLAL, SMULL, or Smlal UMULL, UMLAL, Smull and SmlalUmull Use the top end bits 3116 of Rm SMULxyUse the top end bits 3116 of Rs Are the ARM registers holding the values to be multipliedSmulbt Is the ARM register holding the value to be added SMLAxySmlatb SMULWy Use the top end bits 3116 of RsAre the ARM registers holding the operands SMLAWy Are the ARM registers holding the values to be multipliedIs the ARM register holding the value to be added Smlawt SMLALxy Smlaltt Current processors 8 MIA, MIAPH, and MIAxyUse the top end bits 3116 of Rm R15 cannot be used for either Rm or RsThese instructions are only available in XScale QADD, QSUB, QDADD, and Qdsub ARM saturating arithmetic instructionsIs one of QADD, QSUB, QDADD, or Qdsub Are the ARM registers holding the operandsQadd ARM branch instructions Branch, and Branch with Link 2 BX 3 BLX Blxmi MCR, MCR2, Mcrr on ARM coprocessor instructions1 CDP, CDP2 Is p n, where n is an integer in the range 2 MCR, MCR2, McrrAre ARM source registers. They must not be r15 Affected 3 MRC, MRC2Mrrc Is either LDC or STC 5 LDC, STCIs an optional suffix specifying a long transfer Is the coprocessor register to load or saveArchitectures Is either LDC2 or STC2 6 LDC2, STC2Architectures Miscellaneous ARM instructions Software interrupt 1 SWIWhere 2 MRSIs the destination register. Rd must not be r15 Is either Cpsr or Spsr3 MSR Is either Cpsr or SpsrSee MRS on MSR CPSRf, r5 Breakpoint Bkpt5 MAR, MRA For current processorsAre general-purpose registers ADR ARM pseudo-instructionon ARM pseudo-instructionsAdrl ARM pseudo-instructionon LDR ARM pseudo-instruction onIs an optional condition code ADR ARM pseudo-instructionIs the register to load Non word-aligned address within ±255 bytesAdrl ARM pseudo-instruction Non word-aligned address within 64KBWord-aligned address within 256KB R4,start + = ADD R4,pc,#0xe800 LDR ARM pseudo-instruction R3,=0xff0 Loads Into = MOV r3,#0xff0 NOP ARM pseudo-instruction Thumb Instruction Reference Add with carry Rotate right LDR and STR, immediate offset on Thumb memory access instructionsLDR and STR, register offset on LDR and STR, pc or sp relative onLDR and STR, immediate offset Where Is eitherLoad register Store registerAddress alignment for word and halfword transfers LDR and STR, register offset Strsh 4 in the range 0 to LDR and STR, pc or sp relativeR2,pc,#1016 POP reglist These instructions do not affect the flags POP reglist, pcLoad and store multiple registers Ldmia and StmiaLoad multiple, increment after Store multiple, increment afterR3!, r0,r4 ADD and SUB, sp on Thumb arithmetic instructionsADD, pc or sp relative on ADC, SBC, and MUL onADD and SUB, low registers To +7255 to +255 Restrictions These instructions update the N, Z, C, and V flagsIs a register containing the second operand 2 ADD, high or low registersRange -508 to +508 ADD and SUB, spIs the destination register. Rd must be in the range r0- r7 4 ADD, pc or sp relativeIs either sp or pc Range5 ADC, SBC, and MUL Where Is one of ADC, SBC, or MULCMP and CMN on page 5-26 Compare and Compare Negative Thumb general data processing instructionsMOV, MVN, and NEG on page 5-28 Move, Move NOT, and Negate TST on page 5-30 Test bits1 AND, ORR, EOR, and BIC Where Is one of AND, ORR, EOR, or BICBitwise logical operations Range r0- r72 ASR, LSL, LSR, and ROR Immediate shift Register-controlled shiftWhere Is the register containing the first operand Examples 4 MOV, MVN, and NEG Where Is the destination registerMove, Move NOT, and Negate Is the source registerCondition flags 5 TST Where Is the register containing the first operandTest bits Rn and Rm must be in the range r0-r7Thumb branch instructions Is an optional condition code see -2 on 1 B3-23 for more information Label must be withinCondition codes for Thumb B instruction Long branch with Link 2 BL3 BX Branch with Link, and optionally exchange instruction set 4 BLXInstruction clears the T flag in the CPSR. Code at BLX label always causes a change to ARM stateBkpt on Thumb software interrupt and breakpoint instructionsBkpt immed8 Thumb pseudo-instructions 1KB. expr must be defined locally, it cannot be imported ADR Thumb pseudo-instructionLDR Thumb pseudo-instruction If the value of expr is within range of a MOV instruction,Assembler generates the instruction =labelname Syntax for NOP is NOP Thumb pseudo-instructionARM DUI 0068B Vector Floating-point Programming Absolute value Vector All Negate Vector All Vector floating-point coprocessor Reference ManualVFP architectures Register banks Floating-point registersVector wrap-around VectorsVector stride Restriction on vector lengthControl of scalar, vector and mixed operations Vector and scalar operationsScalar operations Vector operationsVFP and condition codes Vector Floating-point Programming FPSCR, the floating-point status and control register VFP system registers0b000 FPSID, the floating-point system ID register FPEXC, the floating-point exception registerModifying individual bits of a VFP system register See FMRX, FMXR, and Fmstat onFlush-to-zero mode When to use flush-to-zero modeEffects of using flush-to-zero mode Operations not affected by flush-to-zero mode Fmrrs and Fmsrr on VFP instructionsFMRX, FMXR, and Fmstat on Ftosi and Ftoui onPage Fabsd d3, d5 Fnegsmi s15, s15 Is the VFP register for the result Fadd and FsubIs the VFP register holding the first operand Is the VFP register holding the second operandFloating-point compare Fcmp is always scalar FcmpWith zero instruction Fcmp instructions can produce Invalid Operation exceptionsFcvtds Is a double-precision VFP register for the resultIs a single-precision VFP register holding the operand Fcvtsd Is a single-precision VFP register for the resultIs a double-precision VFP register holding the operand Fdiv Floating-point load and store FLD and FSTPrecision specified in precision Address used for the transferFldsne Fldm and Fstm Following instructions are equivalent Unspecified precisionMust be one of FMAC, FNMAC, FMSC, or Fnmsc FMAC, FNMAC, FMSC, and FnmscFnmscsle Is the VFP double-precision register Fmdrr and FmrrdAre ARM registers. Do not use r15 These instructions do not produce any exceptionsFMDHR, FMDLR, FMRDH, and Fmrdl Is the ARM register. Rd must not be r15These instructions are used together as matched pairs Is the VFP single-precision register Fmrs and FmsrFmrrs and Fmsrr Are two consecutive VFP single-precision registersAre the ARM registers. Do not use r15 Is the ARM register FMRX, FMXR, and FmstatFmul and Fnmul Fsito and Fuito Is the VFP register holding the operand FsqrtIs a single-precision VFP register for the integer result Ftosi and FtouiThere is one VFP pseudo-instruction VFP pseudo-instructionFLD pseudo-instruction Can be S for single-precision, or D for double-precisionD1,=3.12E106 Loads 3.12E106 into d1 Vfpassert Scalar on Vfpassert Vector on VFP directives and vector notationVFP directives and vector notation on Vfpassert Vector on Vfpassert ScalarVFP directives and vector notation on Vfpassert Scalar on Where Is the vector length Is the vector strideR10,FPSCR ARM DUI 0068B Conditional assembly, looping, inclusions, and macros Assembly control directives onLocation of descriptions of directives Alphabetical list of directivesThis section describes the following directives Symbol definition directivesGBLA, GBLL, and Gbls on Declare a global arithmetic, logical, or string variableGBLA, GBLL, and Gbls Armasm -pd objectsize Seta 0xFF -o objectfile sourcefile LCLA, LCLL, and Lcls SETA, SETL, and Sets Names on RlistCN directive defines a name for a coprocessor register 5 CNCoprocessor names on Evaluates to a coprocessor register number from 0 toEvaluates to a coprocessor number from 0 to 6 CPDN and SN Evaluates to a floating-point register number from 0 to 8 FNData definition directives DCD and Dcdu onDCQ and Dcqu on Ltorg Is a numeric or program-relative expression 2 MAPSet to this address During the first pass of the assemblerField By the value of exprStorage counter Expressions on SpaceTo 255 see Numeric expressions on 5 DCBQuoted string. The characters of the string are loaded into Consecutive bytes of storeNumeric expression see Numeric expressions on DCD and DcduProgram-relative expression DCW and Dcwu on DCQ and Dcqu onDcdo Dcfd and Dcfdu Dcfs and Dcfsu Is a numeric expression see Numeric expressions on 10 DCIDCD and Dcdu on DCW and Dcwu on DCQ and DcquTo 65535 see Numeric expressions on DCW and DcwuDCD and Dcdu on DCQ and Dcqu on DataMacro and Mend on Assembly control directivesMexit on IF, ELSE, and Endif on While and Wend onMacro and Mend BGE Mexit Using a macro to produce assembly-time diagnosticsSee Relational operators on 4 IF, ELSE, and EndifExample 7-3 Assembly conditional on a variable being defined While and Wend Frame description directives Frame Register on Frame Restore onFrame Address on Frame POP on Frame Push onCan omit it Is sp unless the function uses a separate frame pointerIs the number of bytes that the stack pointer moves There are two alternative syntaxes for Frame POPThere are two alternative syntaxes for Frame Push Frame PushIs the register in which the value is preserved Frame RegisterFrame Restore Frame Save Frame State Remember Frame State Restore on Function or Proc onFrame State Remember on Function or Proc on Frame State RestoreFunction or Proc Endfunc or Endp Reporting directives AssertIs an assertion that can evaluate to either True or False Is an expression that evaluates to a string InfoWhere Is the OPT directive setting. -2 lists valid settings 3 OPTSpecify the -listassembler option to turn on listing OPT TTL and Subt Is the titleIs the subtitle CODE16 and CODE32 on Miscellaneous directivesExport or Global on GET or Include onAlign Cacheable, CODE, ALIGN=3 Area Example,CODE,READONLY An example code section CODE16 and CODE32 4 END Entry directive declares an entry point to a program Entry6 EQU Is the symbolic name to assign to the valueAddress, or a 32-bit integer constant Is optional. type can be any oneExport or Global Exportas Extern Nesting directives on GET or IncludeGlobal File, or library. The symbol name is case-sensitiveSee Export or Global on ImportIncbin IncludeSee GET or Include on Keep Symbols are kept except register-relative symbolsNofp Assembly failsRequire Require directive specifies a dependency between sectionsREQUIRE8 and PRESERVE8 Evaluates to a register number from 0 to 19 RNRout Among other things, computer software See ARM Developer SuiteThumb state PlatformsDefault thread runs Used to find errors in the application program flowSee also Saved Processor Status Register Otherwise statedSee also Rwpi See also RopiSee Read Only Position Independent See Read Write Position IndependentBlock of software code or data for an Image Normally set to zero on resetBy ARM to handle semihosting See Saved Processor Status RegisterIndex Align Gbll Adrl Symbols Index-6