ARM VERSION 1.2 manual SMLAWy, Are the ARM registers holding the values to be multiplied

ARM Instruction Reference

4.4.6SMLAWy

Signed multiply-accumulate (32-bit by 16-bit, top 32-bit accumulate).

Syntax

SMLAW<y>{cond} Rd, Rm, Rs, Rn

where:

<y>
	is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means
	use the top end (bits [31:16]) of Rs.
cond	is an optional condition code (see Conditional execution on page 4-4).
Rd	is the ARM register for the result.
Rm, Rs	are the ARM registers holding the values to be multiplied.
Rn	is the ARM register holding the value to be added.

r15 cannot be used for any of Rd, Rm, Rs, or Rn.

Any combination of Rd, Rm, Rs, and Rn can use the same registers.

Usage

The SMLAWy instruction multiplies the signed integer from the selected half of Rs by the signed integer from Rm, adds the 32-bit result to the 32-bit value in Rn, and places the result in Rd.

Condition flags

This instruction does not affect the N, Z, C or V flags.

If overflow occurs in the accumulation, it sets the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS on page 4-73).

Note

This instruction never clears the Q flag. To clear the Q flag, use an MSR instruction (see MSR on page 4-74).

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