ARM Instruction Reference
4-42 Copyright © 2000, 2001 ARM Limited. A ll rights reserved. ARM DUI 0068B
4.4.2 UMULL, UMLAL, SMULL and SMLAL
Unsigned and signed long multiply and multiply accumulate (32-bit by 32-bit, 64-bit
accumulate or resu lt).
Syntax
Op{cond}{S} RdLo, RdHi, Rm, Rs
where:
Op
is one of
UMULL
,
UMLAL
,
SMULL
, or
SMLAL
.
cond
is an optional condition code (see Conditional execution on page4-4).
S
is an optional suffix. If
S
is specified, the condition code flags are updated
on the result of the operation (see Conditional execution on page4-4).
RdLo, RdHi
are ARM registers for the result. For
UMLAL
and
SMLAL
they also hold the
accumulating value.
Rm, Rs
are ARM registers holding the operands.
r15 cannot be used for any of
RdHi
,
RdLo
,
Rm
, or
Rs
.
RdLo
,
RdHi
, and
Rm
must all be different registers.
Usage
The
UMULL
instruction interprets the values from
Rm
and
Rs
as unsigned integers. It
multiplies these integers and places the least significant 32 bits of the result in
RdLo
, and
the most significant 32 bits of the result in
RdHi
.
The
UMLAL
instruction interprets the values from
Rm
and
Rs
as unsigned integers. It
multiplies these integers, and adds the 64-bit result to the 64-bit unsigned integer
contained in
RdHi
and
RdLo
.
The
SMULL
instruction interprets the values from
Rm
and
Rs
as two’s complement signed
integers. It multiplies these integers and places the least significant 32 bits of the result
in
RdLo
, and the most significant 32 bits of the result in
RdHi
.
The
SMLAL
instruction interprets the values from
Rm
and
Rs
as two’s complement signed
integers. It multiplies these integers, and adds the 64-bit result to the 64-bit signed
integer contained in
RdHi
and
RdLo
.