ARM VERSION 1.2 8 MIA, MIAPH, and MIAxy, Current processors, Use the top end bits 3116 of Rm

ARM Instruction Reference

4.4.8MIA, MIAPH, and MIAxy

XScale coprocessor 0 instructions.

Multiply with internal accumulate (32-bit by 32-bit, 40-bit accumulate).

Multiply with internal accumulate, packed halfwords (16-bit by 16-bit twice, 40-bit accumulate).

Multiply with internal accumulate (16-bit by 16-bit, 40-bit accumulate).

Syntax

MIA{cond} Acc, Rm, Rs MIAPH{cond} Acc, Rm, Rs MIA<x><y>{cond} Acc, Rm, Rs where:

cond	is an optional condition code (see Conditional execution on page 4-4).
Acc	is the internal accumulator. The standard name is accx, where x is an
	integer in the range 0-n. The value of n depends on the processor. It is 0
	in current processors.
Rm, Rs	are the ARM registers holding the values to be multiplied.
<x>
	is either B or T. B means use the bottom end (bits [15:0]) of Rm, T means
	use the top end (bits [31:16]) of Rm.
<y>
	is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means
	use the top end (bits [31:16]) of Rs.

r15 cannot be used for either Rm or Rs.

Usage

The MIA instruction multiplies the signed integers from Rs and Rm, and adds the result to the 40-bit value in Acc.

The MIAPH instruction multiplies the signed integers from the lower halves of Rs and Rm, multiplies the signed integers from the upper halves of Rs and Rm, and adds the two 32-bit results to the 40-bit value in Acc.

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