ARM VERSION 1.2

Writing ARM and Thumb Assembly Language

2.2.7 Thumb instruction set overview

The functionality of the Thumb instruction set is almost exactly a subset of the

functionality of the ARM instruction set. The instruction set is optimized for production

by a C or C++ compiler.

All Thumb instructions are 16 bits long and are stored halfword-aligned in memory.

Because of this, the least significant bit of the address of an instruction is always zero

in Thumb state. Some instructions use the least significant bit to determine whether the

code being branched to is Thumb code or ARM code.

All Thumb data processing instructions:

•operate on full 32-bit values in registers

•use full 32-bit addresses for data access and for instruction fetches.

Refer to Chapter5 Thumb Instruction Reference for detailed information on the syntax

of the Thumb instruction set, and how Thumb instructions differ from their ARM

counterparts.

2.2.8 Thumb instruction capabilities

The following general points apply to Thumb instructions:

•Conditional execution

•Register access

•Access to the barrel shifter on page 2-10.

Conditional execution

The conditional branch instruction is the only Thumb instruction that can be executed

conditionally on the value of the ALU status flags in the CPSR. All data processing

instructions update these flags, except when one or more high registers are specified as

operands to the

MOV

ADD

instructions. In the se cases the flags cannot be updated.

You cannot have any data processing instructions between an instruction that sets a

condition and a conditional branch that depends on it. Use a conditional branch over any

instruction that you wish to be conditional.

In Thumb state, most instructions can access only r0 to r7. These are referred to as the

low registers.

Registers r8 to r15 ar e limited access reg isters. In Thumb stat e these are referred to as

high registers. They can be used, for example, as fast temporary storage.