Assembler Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All r ights reserved. 3-9
3.3 Predefined register and coprocessor names
All register and coprocessor names are case-sensitive.
3.3.1 Predeclared register names
The following register names are predeclared:
•
r0-r15
and
R0-R15
•
a1-a4
(argument, result, or scratch registers, synonyms for r0 to r3)
•
v1-v8
(variable registers, r4 to r11)
•
sb
and
SB
(static base, r9)
•
sl
and
SL
(stack limit, r10)
•
fp
and
FP
(frame pointer, r11)
•
ip
and
IP
(intra-procedure-call scratch register, r12)
•
sp
and
SP
(stack pointer, r13)
•
lr
and
LR
(link register, r14)
•
pc
and
PC
(program counter, r15).
3.3.2 Predeclared program status register names
The following program status register names are predeclared:
•
cpsr
and
CPSR
(current program status register)
•
spsr
and
SPSR
(saved program status register).
3.3.3 Predeclared floating-point register names
The following floating-point register names are predeclared:
•
f0-f7
and
F0-F7
(FPA registers)
•
s0-s31
and
S0-S31
(VFP single-precision registers)
•
d0-d15
and
D0-D15
(VFP double-precision registers).
3.3.4 Predeclared coprocessor names
The following coprocessor names and coprocessor register names are predeclared:
•
p0-p15
(coprocessors 0-15)
•
c0-c15
(coprocessor registers 0-15).