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Figure 42. FXO Loop Start – Incoming Clear Timing Diagram

IISDN SMI MESSAGES:

L4L3mCLEAR_REQUEST

L3L4mDISCONNECT L3L4mCLEAR_REQUEST

IISDN TIMERS:

hooktimer_onhook_rls

hooktimer_offhook_inseize

guard_interval_timer

ign_insz_post_rls_timer

delayed_onhook_timer

hooktimer_onhook_rls

RECEIVED BITS,

A Bit

B Bit

TRANSMITTED

A Bit

B Bit

NOTE: This diagram is designed to give the reader a general understanding of the sequence of events for this robbed

bit protocol over time. The timers and spacing on this graph are not proportional to the actual events that occur.

Revised 10-Nov-98

Revision 1.3

Loop Start Signaling

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Image 308
Dialogic 6.2 manual FXO Loop Start Incoming Clear Timing Diagram, November 308