Intel 31154 133 MHz PCI Bridge Design Guide | Intel instruction

Intel® 31154 133 MHz PCI Bridge Design Guide

Design Guide

April 2004

Order Number: 278944-001

Image 1

Intel manual Intel 31154 133 MHz PCI Bridge Design Guide

Contents

Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Contents Tables Figures Contents Date Revision Description Revision History001 Initial release Terminology and Definitions About This DocumentTerminology and Definition Sheet 1 Definition Term Terminology and Definition Sheet 2ISI SHB Introduction2 PCI-to-PCI Bridge ConfigurationsProduct Overview Intel 31154 133 MHz PCI Bridge Applications Features List Features List References Related External Specifications This page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals Jtag This page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4 Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI Signals PCI Clocks Pull-Up/Pull-Down Terminations Sheet 3 Hot Swap Pull-Up/Pull-Down Terminations Sheet 4 Pull-Up/Pull-Down Terminations Sheet 5 SarbdisableHardware Straps sampled at the edge of PRST# Sarblock Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 6 Voltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous RSTV0 Pull-Up/Pull-Down Terminations Sheet 8RSRV1/CRSTEN SM66EN NTMASK# Pull-Up/Pull-Down Terminations Sheet 9 This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfaceInterrupt Routing PCI/PCI-X Voltage Levels Primary Idsel Line Idsel LinesSecondary Idsel Lines Opaque Memory Region Enable CompactPCI* Hot Swap Mode SelectSecondary Idsel Masking Secondary Clock Control Secondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND PCI-X Initialization Pattern Primary-to-Secondary Frequency LimitsClock Frequency MHz Routing Guidelines Crosstalk Effects on Trace Distance and Height Crosstalk EMI Considerations PCB Ground Layout Around Connectors Pins Voltage Capacitor Value Number Power Distribution and DecouplingDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling Recommendations Trace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout Guidelines PCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout Guidelines Single Slot at 133 MHz Wiring Lengths for 133 MHz SlotLower AD Bus Upper AD Bus Segment Maximum Lower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz Design Dual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-Slot Wiring Lengths for Embedded 100 MHz Design Quad-Slots at 66 MHz Wiring Lengths for 66 MHz Quad-Slot Sheet 1W13 W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz Design PCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 Overview An Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 Backplane Clock Point to Point PCI-X Clock Wiring Lengths for Picmg Backplane This page Intentionally Left Blank Analog Power Pins Power Considerations Power Sequencing Eeprom Customer Reference Board Customer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10 Logic Analyzer Pod Devsel FrameTrdy BE2 Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Related Documents References12Design Reference Material Design Reference Material References