Manuals / Intel / Computer Equipment / Computer Hardware

Intel 31154 manual Terminology and Definition Sheet 2 of, About This Document

Models: 31154

1 72

Download 72 pages 37.2 Kb

Page 8

Table 1. Terminology and Definition (Sheet 2 of 2)

About This Document

Table 1. Terminology and Definition (Sheet 2 of 2)

Term	Definition

An aggressor network is a network that transmits a coupled signal to another network.

	Aggressor	Zo		Zo

		Victim Network
		Zo		Zo


		Aggressor Network
				B3337-01

	Victim	A network that receives a coupled cross-talk signal from another network is a called the victim
	Victim	network.
		network.

	Network	A network is the trace of a PCB that completes an electrical connection between two or more
	Network	components.
		components.

	Stub	A stub is a branch from a trunk terminating at the pad of an agent.

		Inter-Symbol Interference (ISI) occurs when a transition that has not been completely
		dissipated interferes with a signal being transmitted down a transmission line. ISI can impact
		both timing and signal integrity. It is dependent on frequency, time delay of the line, and the
		refection coefficient at the driver and receiver. Examples of ISI patterns that can be used in
	ISI	testing at the maximum allowable frequencies are the sequences shown below:
		0101 0101 0101 0101
		0011 0011 0011 0011
		000 1110 0011 1000 1111

	Device	A device is a component of a PCI system that connects to a PCI bus. As defined by PCI 2.3,
	Device	a device can be a single-function or a multi-function device.


	Downstream	A transaction that targets the secondary side of the bridge is a downstream transaction.

	Upstream	A transaction that targets the primary side of the bridge is an upstream transaction.

	SHB	SHB is a system host board in a PICMIG 1.2 backplane. The removable CPU board provides
	SHB	clocks and arbitration signals as well as an optional ATX power supply control.


	ePCI-X	Embedded PCI-X specification

	CRB	Customer Reference Board

§ §

8	Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 8

Intel 31154 manual Terminology and Definition Sheet 2 of, About This Document

Contents

April Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide ContentsContents Figures TablesContents Intel 31154 133 MHz PCI Bridge Design GuideContents Intel 31154 133 MHz PCI Bridge Design GuideRevision History ContentsIntel 31154 133 MHz PCI Bridge Design Guide DateAbout This Document 1.1 Terminology and DefinitionsAbout This Document Terminology and Definition Sheet 1 ofTable 1. Terminology and Definition Sheet 2 of About This DocumentIntel 31154 133 MHz PCI Bridge Design Guide Design Guide TermPCI-to-PCI Bridge Configurations Introduction22.1 Product Overview Introduction2.2 Features List Features ListPCI Local Bus Specification, Revision 2.3 compliant PCI-to-PCI Bridge Architecture Specification, Revision 1.2 compliant2.3 Related External Specifications PCI Local Bus Specification, RevisionPCI-to-PCI Bridge Architecture Specification, Revision PCI Bus Power Management Interface Specification, RevisionIntel 31154 133 MHz PCI Bridge Design Guide Design Guide THIS PAGE INTENTIONALLY LEFT BLANKIntroduction Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationPackage Information Figure 2. Intel 31154 133 MHz PCI Bridge Package Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide BOTTOM VIEWFigure 3. Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide AC VSSPackage Information Intel 31154 133 MHz PCI Bridge Design Guide Design Guide13 14 15 16 17 18 19 20 VCCA3.1 Total Signal Count Total Signal CountSignals Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationTHIS PAGE INTENTIONALLY LEFT BLANK Terminations4 TerminationsPull-Up/Pull-Down Terminations Sheet 1 of Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePull-Up/Pull-Down Terminations Sheet 2 of SignalSecondary PCI Signals TerminationsPull-Up/Pull-Down Terminations Sheet 3 of SignalTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePull-Up/Pull-Down Terminations Sheet 4 of SignalTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePull-Up/Pull-Down Terminations Sheet 5 of Signalresistor default TerminationsPull-Up/Pull-Down Terminations Sheet 6 of SignalTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePull-Up/Pull-Down Terminations Sheet 7 of Signal“Power Sequencing” on page “Power Sequencing” on pagePull-Up/Pull-Down Terminations Sheet 8 of SignalTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePull-Up/Pull-Down Terminations Sheet 9 of SignalTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide TerminationsTHIS PAGE INTENTIONALLY LEFT BLANK PCI/PCI-X Interface 5.1 PCI/PCI-X Voltage Levels5.2 Interrupt Routing PCI/PCI-X Interface5.3 IDSEL Lines 5.3.1 Primary IDSEL Line5.3.2 Secondary IDSEL Lines IDSEL Mapping5.5 Opaque Memory Region Enable 5.3.3 Secondary IDSEL Masking5.4 CompactPCI* Hot Swap Mode Select 5.3.4 Secondary Clock Control5.6 PCI-X Initialization Clocking Modes 5.6.1 Primary PCI Clocking Mode5.6.2 Secondary PCI Clocking Mode PCI/PCI-X InterfacePCI-X Clocking Modes Secondary Bus Frequency InitializationPCI/PCI-X Interface Intel 31154 133 MHz PCI Bridge Design Guide Design Guide5.6.3 Primary-to-Secondary Frequency Limits PCI-X Initialization PatternPCI/PCI-X Interface Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesRouting Guidelines 6.1 Crosstalk Figure 6. Crosstalk Effects on Trace Distance and HeightRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideFigure 7. PCB Ground Layout Around Connectors 6.2 EMI ConsiderationsRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide6.3 Power Distribution and Decoupling 6.3.1 Decoupling RecommendationsTable 11. Intel 31154 133 MHz PCI Bridge Decoupling Recommendations Routing GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 6.4 Trace ImpedanceRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK PCI-X Layout Guidelines PCI-X Layout GuidelinesAdd-in Card Routing Parameters Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 7.1 PCI Clock Layout GuidelinesPCI-X Layout Guidelines #### Intel####%,%!#%# Notes -3%%%7.2 PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideWiring Lengths for 133 MHz Slot 7.2.1 Single Slot at 133 MHzFigure 9. Single-Slot Point-to-Point Topology PCI-X Layout GuidelinesWiring Lengths for Embedded 133 MHz Design PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide B3058-01Figure 11. Dual-Slot Configuration Wiring Lengths for 100 MHz Dual-Slot7.2.2 Dual-Slot at 100 MHz PCI-X Layout GuidelinesWiring Lengths for Embedded 100 MHz Design PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Lower AD BusTable 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 1 of 7.2.3 Quad-Slots at 66 MHzFigure 13. Quad-Slots 66 MHz Topology PCI-X Layout GuidelinesTable 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 2 of PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Lower AD BusFigure 14. Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz Wiring Lengths for Embedded 66 MHz Design7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz PCI-X Layout Guidelines7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview 7.2.4 PCI-X at 33 MHz7.2.4.2 PICMG 1.2 System Overview PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 15. An Example of an ePCI-X SystemPCI-X Layout Guidelines Table 20. Wiring Lengths for PICMG 1.2 Backplane Figure 16. PCI-X Data Bus PICMG 1.2 Style BackplanePCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTable 21. PCI-X Clock Wiring Lengths for PICMG Backplane Figure 17. PCI-X Clock PICMG 1.2 Style BackplaneSlot1 SlotNIntel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Layout GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK Power Considerations 8.1 Analog Power PinsPower Considerations Intel 31154 133 MHz PCI Bridge Design Guide Design Guide8.2 Power Sequencing Intel 133 MHz PCI BridgePower Considerations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideFigure 21. Intel IQ31154 Customer Reference Board Block Diagram Customer Reference BoardIntel 133 MHz PCI BridgeIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Customer Reference Board StackupCustomer Reference Board Debug Connectors and Logic Analyzer Connectivity10 10.1 Probing PCI-X SignalsDebug Connectors and Logic Analyzer Connectivity Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Logic Analyzer PodDebug Connectors and Logic Analyzer Connectivity Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Debug Connectors and Logic Analyzer Connectivity Logic Analyzer PodIntel 31154 133 MHz PCI Bridge Design Guide Design Guide AD15Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Debug Connectors and Logic Analyzer Connectivity PCI-X Signal NameLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design GuideDebug Connectors and Logic Analyzer Connectivity The recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5 from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does notLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityTHIS PAGE INTENTIONALLY LEFT BLANK Thermal Solutions Thermal SolutionsTable 29. Operational Power Maximum PowerIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Thermal SolutionsTHIS PAGE INTENTIONALLY LEFT BLANK References12 12.1 Related DocumentsReferences Table 30. Design Reference MaterialIntel 31154 133 MHz PCI Bridge Design Guide Design Guide ReferencesTHIS PAGE INTENTIONALLY LEFT BLANK