Design Guide
Intel 31154 133 MHz PCI Bridge Design Guide
April
Intel 31154 133 MHz PCI Bridge Design Guide
Contents
Contents
Intel 31154 133 MHz PCI Bridge Design Guide
Contents
Figures
Tables
Intel 31154 133 MHz PCI Bridge Design Guide
Contents
Intel 31154 133 MHz PCI Bridge Design Guide
Intel 31154 133 MHz PCI Bridge Design Guide
Revision History
Contents
Date
About This Document
About This Document
1.1 Terminology and Definitions
Terminology and Definition Sheet 1 of
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Table 1. Terminology and Definition Sheet 2 of
About This Document
Term
2.1 Product Overview
PCI-to-PCI Bridge Configurations
Introduction2
Introduction
PCI Local Bus Specification, Revision 2.3 compliant
2.2 Features List
Features List
PCI-to-PCI Bridge Architecture Specification, Revision 1.2 compliant
PCI-to-PCI Bridge Architecture Specification, Revision
2.3 Related External Specifications
PCI Local Bus Specification, Revision
PCI Bus Power Management Interface Specification, Revision
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Introduction
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Package Information
Package Information
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Figure 2. Intel 31154 133 MHz PCI Bridge Package
Package Information
BOTTOM VIEW
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Figure 3. Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side
Package Information
AC VSS
13 14 15 16 17 18 19 20
Package Information
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
VCCA
Signals
3.1 Total Signal Count
Total Signal Count
Package Information
Package Information
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Pull-Up/Pull-Down Terminations Sheet 1 of
Terminations4
Terminations
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Secondary PCI Signals
Pull-Up/Pull-Down Terminations Sheet 2 of
Signal
Terminations
Terminations
Pull-Up/Pull-Down Terminations Sheet 3 of
Signal
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Terminations
Pull-Up/Pull-Down Terminations Sheet 4 of
Signal
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
resistor default
Pull-Up/Pull-Down Terminations Sheet 5 of
Signal
Terminations
Terminations
Pull-Up/Pull-Down Terminations Sheet 6 of
Signal
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
“Power Sequencing” on page
Pull-Up/Pull-Down Terminations Sheet 7 of
Signal
“Power Sequencing” on page
Terminations
Pull-Up/Pull-Down Terminations Sheet 8 of
Signal
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Terminations
Pull-Up/Pull-Down Terminations Sheet 9 of
Signal
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Terminations
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
5.2 Interrupt Routing
PCI/PCI-X Interface
5.1 PCI/PCI-X Voltage Levels
PCI/PCI-X Interface
5.3.2 Secondary IDSEL Lines
5.3 IDSEL Lines
5.3.1 Primary IDSEL Line
IDSEL Mapping
5.4 CompactPCI* Hot Swap Mode Select
5.5 Opaque Memory Region Enable
5.3.3 Secondary IDSEL Masking
5.3.4 Secondary Clock Control
5.6.2 Secondary PCI Clocking Mode
5.6 PCI-X Initialization Clocking Modes
5.6.1 Primary PCI Clocking Mode
PCI/PCI-X Interface
PCI/PCI-X Interface
PCI-X Clocking Modes
Secondary Bus Frequency Initialization
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
PCI/PCI-X Interface
5.6.3 Primary-to-Secondary Frequency Limits
PCI-X Initialization Pattern
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Routing Guidelines
Routing Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Routing Guidelines
6.1 Crosstalk
Figure 6. Crosstalk Effects on Trace Distance and Height
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Routing Guidelines
Figure 7. PCB Ground Layout Around Connectors
6.2 EMI Considerations
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Table 11. Intel 31154 133 MHz PCI Bridge Decoupling Recommendations
6.3 Power Distribution and Decoupling
6.3.1 Decoupling Recommendations
Routing Guidelines
6.4 Trace Impedance
Routing Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Routing Guidelines
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Add-in Card Routing Parameters
PCI-X Layout Guidelines
PCI-X Layout Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
7.1 PCI Clock Layout Guidelines
PCI-X Layout Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
####%,%!#%#
####
Intel
Notes -3%%%
PCI-X Layout Guidelines
7.2 PCI-X Topology Layout Guidelines
PCI-X Slot Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Figure 9. Single-Slot Point-to-Point Topology
Wiring Lengths for 133 MHz Slot
7.2.1 Single Slot at 133 MHz
PCI-X Layout Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Wiring Lengths for Embedded 133 MHz Design
PCI-X Layout Guidelines
B3058-01
7.2.2 Dual-Slot at 100 MHz
Figure 11. Dual-Slot Configuration
Wiring Lengths for 100 MHz Dual-Slot
PCI-X Layout Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Wiring Lengths for Embedded 100 MHz Design
PCI-X Layout Guidelines
Lower AD Bus
Figure 13. Quad-Slots 66 MHz Topology
Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 1 of
7.2.3 Quad-Slots at 66 MHz
PCI-X Layout Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 2 of
PCI-X Layout Guidelines
Lower AD Bus
7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz
Figure 14. Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz
Wiring Lengths for Embedded 66 MHz Design
PCI-X Layout Guidelines
7.2.4.2 PICMG 1.2 System Overview
7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview
7.2.4 PCI-X at 33 MHz
PCI-X Layout Guidelines
Figure 15. An Example of an ePCI-X System
PCI-X Layout Guidelines
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
PCI-X Layout Guidelines
Table 20. Wiring Lengths for PICMG 1.2 Backplane
Figure 16. PCI-X Data Bus PICMG 1.2 Style Backplane
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Slot1
Table 21. PCI-X Clock Wiring Lengths for PICMG Backplane
Figure 17. PCI-X Clock PICMG 1.2 Style Backplane
SlotN
PCI-X Layout Guidelines
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Power Considerations
Power Considerations
8.1 Analog Power Pins
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Power Considerations
8.2 Power Sequencing
Intel 133 MHz PCI Bridge
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Intel
Figure 21. Intel IQ31154 Customer Reference Board Block Diagram
Customer Reference Board
133 MHz PCI Bridge
Customer Reference Board Stackup
Customer Reference Board
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Debug Connectors and Logic Analyzer Connectivity
Debug Connectors and Logic Analyzer Connectivity10
10.1 Probing PCI-X Signals
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Logic Analyzer Pod
Debug Connectors and Logic Analyzer Connectivity
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Debug Connectors and Logic Analyzer Connectivity
Logic Analyzer Pod
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Debug Connectors and Logic Analyzer Connectivity
Logic Analyzer Pod
AD15
Debug Connectors and Logic Analyzer Connectivity
Logic Analyzer Pod
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Logic Analyzer Pod
Debug Connectors and Logic Analyzer Connectivity
PCI-X Signal Name
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Logic Analyzer Pod
Debug Connectors and Logic Analyzer Connectivity
The recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5 from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does not
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Debug Connectors and Logic Analyzer Connectivity
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
Table 29. Operational Power
Thermal Solutions
Thermal Solutions
Maximum Power
Thermal Solutions
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
References
References12
12.1 Related Documents
Table 30. Design Reference Material
References
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Intel 31154 133 MHz PCI Bridge Design Guide Design Guide