Intel 31154 manual PCI-X Initialization Clocking Modes, Primary PCI Clocking Mode

PCI/PCI-X Interface

5.6PCI-X Initialization Clocking Modes

Both of the PCI bus interfaces can operate at a variety of frequencies, and in either conventional PCI mode, or in PCI-X mode. Each interface establishes the bus mode and frequency when coming out of its corresponding bus segment reset sequence. The resultant mode and frequency is dependent upon the device capabilities reported, in addition to any system-specific loading information.

5.6.1Primary PCI Clocking Mode

The 31154 reports its primary bus operating capabilities to the originating device (typically the host bridge) of the primary bus segments. The 31154 indicates to the originating device of the primary bus segments that its primary interface is PCI-X–capable at frequencies of up to 133 MHz. It also indicates that the 31154 is capable of running at 66 MHz when operating in conventional PCI mode.

5.6.2Secondary PCI Clocking Mode

The 31154 is the originating device for its secondary bus, and as such sets the bus mode and frequency when exiting out of the secondary bus reset sequence. The two key components that factor into the resultant secondary bus mode and frequency are the PCI-X standard sampling of downstream device capabilities, and the system-specific physical bus loading characteristics for which the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b does not provide any standard means of reporting.

Downstream device capabilities are indicated by the values of S_M66EN and S_PCIXCAP during S_RST# assertion. Knowledge of the device capabilities alone is insufficient information to robustly select the bus frequency. In order to know with certainty at what frequency to set the bus, knowledge of the bus layout (for example, the number of slots) is also necessary. The 31154 provides the S_MAX100 strapping pin for reporting system-specific secondary bus loading information that is used in determining the maximum operating frequency of the secondary bus. The 31154 considers S_MAX100 along with S_PCIXCAP and S_M66EN# to determine the secondary bus mode and frequency when emerging from S_RST#. For example, when a card is plugged into a two-slot secondary bus, the S_MAX100 strapping of 1b ensures that the bus runs at no greater than 100 MHz, regardless of the reported downstream device capabilities.

32 Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide