This page Intentionally Left Blank | Intel 31154 specification

Introduction

THIS PAGE INTENTIONALLY LEFT BLANK

12	Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 12

Intel 31154 manual This page Intentionally Left Blank

Contents

Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description001 Initial release About This Document Terminology and DefinitionsTerminology and Definition Sheet 1 Definition Terminology and Definition Sheet 2 TermISI SHB PCI-to-PCI Bridge Configurations Introduction2Product Overview Intel 31154 133 MHz PCI Bridge Applications Features List Features List Related External Specifications References This page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals Jtag This page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1 Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2 Pull-Up/Pull-Down Terminations Sheet 3 PCI Clocks Pull-Up/Pull-Down Terminations Sheet 4 Hot Swap Sarbdisable Pull-Up/Pull-Down Terminations Sheet 5Hardware Straps sampled at the edge of PRST# Sarblock Pull-Up/Pull-Down Terminations Sheet 6 Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous Pull-Up/Pull-Down Terminations Sheet 8 RSTV0RSRV1/CRSTEN SM66EN Pull-Up/Pull-Down Terminations Sheet 9 NTMASK# This page Intentionally Left Blank PCI/PCI-X Interface PCI/PCI-X Voltage LevelsInterrupt Routing PCI/PCI-X Voltage Levels Idsel Lines Primary Idsel LineSecondary Idsel Lines CompactPCI* Hot Swap Mode Select Opaque Memory Region EnableSecondary Idsel Masking Secondary Clock Control Primary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND Primary-to-Secondary Frequency Limits PCI-X Initialization PatternClock Frequency MHz Routing Guidelines Crosstalk Crosstalk Effects on Trace Distance and Height PCB Ground Layout Around Connectors EMI Considerations Power Distribution and Decoupling Pins Voltage Capacitor Value NumberDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling Recommendations Trace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing Parameters PCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot Guidelines Wiring Lengths for 133 MHz Slot Single Slot at 133 MHzLower AD Bus Upper AD Bus Segment Maximum Wiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD Bus Wiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHz Wiring Lengths for Embedded 100 MHz Design Wiring Lengths for 66 MHz Quad-Slot Sheet 1 Quad-Slots at 66 MHzW13 W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum Length Embedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHz An Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus Units PCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to Point This page Intentionally Left Blank Power Considerations Analog Power Pins Power Sequencing Customer Reference Board Eeprom Customer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X Signals Logic Analyzer Pod Frame DevselTrdy BE2 Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions References12 Related DocumentsDesign Reference Material Design Reference Material References