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Intel 31154 manual Logic Analyzer Pod, Debug Connectors and Logic Analyzer Connectivity

Models: 31154

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Debug Connectors and Logic Analyzer Connectivity

Table 23.	Logic Analyzer Pod 1

	Mictor-38 #1 Pin Number Odd Pod	Logic Analyzer Channel Number	PCI-X Name

	6	CLKC/16	CLK

	8	15	C/BE4

	10	14	C/BE5

	12	13	C/BE6

	14	12	C/BE7

	16	11	ACK64

	18	10	REQ64

	20	9	UNUSED

	22	8	PME

	24	7	C/BEO

	26	6	M66EN

	28	5	C/BE1

	30	4	SERR

	32	3	PAR

	34	2	PERR

	36	1	LOCK

	38	0	STOP

62	Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Intel 31154 manual Logic Analyzer Pod, Debug Connectors and Logic Analyzer Connectivity

Contents

April Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide ContentsContents Contents FiguresTables Intel 31154 133 MHz PCI Bridge Design GuideContents Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Revision HistoryContents DateAbout This Document About This Document1.1 Terminology and Definitions Terminology and Definition Sheet 1 ofIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Table 1. Terminology and Definition Sheet 2 ofAbout This Document Term2.1 Product Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 IntroductionPCI Local Bus Specification, Revision 2.3 compliant 2.2 Features ListFeatures List PCI-to-PCI Bridge Architecture Specification, Revision 1.2 compliantPCI-to-PCI Bridge Architecture Specification, Revision 2.3 Related External SpecificationsPCI Local Bus Specification, Revision PCI Bus Power Management Interface Specification, RevisionIntel 31154 133 MHz PCI Bridge Design Guide Design Guide THIS PAGE INTENTIONALLY LEFT BLANKIntroduction Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationPackage Information Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 2. Intel 31154 133 MHz PCI Bridge PackagePackage Information BOTTOM VIEWIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 3. Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left SidePackage Information AC VSS13 14 15 16 17 18 19 20 Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide VCCASignals 3.1 Total Signal CountTotal Signal Count Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationTHIS PAGE INTENTIONALLY LEFT BLANK Pull-Up/Pull-Down Terminations Sheet 1 of Terminations4Terminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSecondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2 ofSignal TerminationsTerminations Pull-Up/Pull-Down Terminations Sheet 3 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTerminations Pull-Up/Pull-Down Terminations Sheet 4 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design Guideresistor default Pull-Up/Pull-Down Terminations Sheet 5 ofSignal TerminationsTerminations Pull-Up/Pull-Down Terminations Sheet 6 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design Guide“Power Sequencing” on page Pull-Up/Pull-Down Terminations Sheet 7 ofSignal “Power Sequencing” on pageTerminations Pull-Up/Pull-Down Terminations Sheet 8 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTerminations Pull-Up/Pull-Down Terminations Sheet 9 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide TerminationsTHIS PAGE INTENTIONALLY LEFT BLANK 5.2 Interrupt Routing PCI/PCI-X Interface5.1 PCI/PCI-X Voltage Levels PCI/PCI-X Interface5.3.2 Secondary IDSEL Lines 5.3 IDSEL Lines5.3.1 Primary IDSEL Line IDSEL Mapping5.4 CompactPCI* Hot Swap Mode Select 5.5 Opaque Memory Region Enable5.3.3 Secondary IDSEL Masking 5.3.4 Secondary Clock Control5.6.2 Secondary PCI Clocking Mode 5.6 PCI-X Initialization Clocking Modes5.6.1 Primary PCI Clocking Mode PCI/PCI-X InterfacePCI/PCI-X Interface PCI-X Clocking ModesSecondary Bus Frequency Initialization Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePCI/PCI-X Interface 5.6.3 Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesRouting Guidelines Routing Guidelines 6.1 CrosstalkFigure 6. Crosstalk Effects on Trace Distance and Height Intel 31154 133 MHz PCI Bridge Design Guide Design GuideRouting Guidelines Figure 7. PCB Ground Layout Around Connectors6.2 EMI Considerations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTable 11. Intel 31154 133 MHz PCI Bridge Decoupling Recommendations 6.3 Power Distribution and Decoupling6.3.1 Decoupling Recommendations Routing GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 6.4 Trace ImpedanceRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 7.1 PCI Clock Layout GuidelinesPCI-X Layout Guidelines ####%,%!#%# ####Intel Notes -3%%%PCI-X Layout Guidelines 7.2 PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideFigure 9. Single-Slot Point-to-Point Topology Wiring Lengths for 133 MHz Slot7.2.1 Single Slot at 133 MHz PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Wiring Lengths for Embedded 133 MHz DesignPCI-X Layout Guidelines B3058-017.2.2 Dual-Slot at 100 MHz Figure 11. Dual-Slot ConfigurationWiring Lengths for 100 MHz Dual-Slot PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Wiring Lengths for Embedded 100 MHz DesignPCI-X Layout Guidelines Lower AD BusFigure 13. Quad-Slots 66 MHz Topology Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 1 of7.2.3 Quad-Slots at 66 MHz PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 2 ofPCI-X Layout Guidelines Lower AD Bus7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz Figure 14. Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHzWiring Lengths for Embedded 66 MHz Design PCI-X Layout Guidelines7.2.4.2 PICMG 1.2 System Overview 7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview7.2.4 PCI-X at 33 MHz PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 15. An Example of an ePCI-X SystemPCI-X Layout Guidelines PCI-X Layout Guidelines Table 20. Wiring Lengths for PICMG 1.2 BackplaneFigure 16. PCI-X Data Bus PICMG 1.2 Style Backplane Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSlot1 Table 21. PCI-X Clock Wiring Lengths for PICMG BackplaneFigure 17. PCI-X Clock PICMG 1.2 Style Backplane SlotNIntel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Layout GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK Power Considerations Power Considerations8.1 Analog Power Pins Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePower Considerations 8.2 Power SequencingIntel 133 MHz PCI Bridge Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel Figure 21. Intel IQ31154 Customer Reference Board Block DiagramCustomer Reference Board 133 MHz PCI BridgeIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Customer Reference Board StackupCustomer Reference Board Debug Connectors and Logic Analyzer Connectivity Debug Connectors and Logic Analyzer Connectivity1010.1 Probing PCI-X Signals Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Logic Analyzer PodDebug Connectors and Logic Analyzer Connectivity Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod AD15Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Logic Analyzer Pod Debug Connectors and Logic Analyzer ConnectivityPCI-X Signal Name Intel 31154 133 MHz PCI Bridge Design Guide Design GuideLogic Analyzer Pod Debug Connectors and Logic Analyzer ConnectivityThe recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5 from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does not Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityTHIS PAGE INTENTIONALLY LEFT BLANK Table 29. Operational Power Thermal SolutionsThermal Solutions Maximum PowerIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Thermal SolutionsTHIS PAGE INTENTIONALLY LEFT BLANK References References1212.1 Related Documents Table 30. Design Reference MaterialIntel 31154 133 MHz PCI Bridge Design Guide Design Guide ReferencesTHIS PAGE INTENTIONALLY LEFT BLANK

Logic Analyzer Pod 1