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Intel manual Routing Guidelines, Intel 31154 133 MHz PCI Bridge Design Guide Design Guide

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	Routing Guidelines
Routing Guidelines	6

This chapter provides some basic routing guidelines for layout and design of a printed circuit board (PCB) using the Intel® 31154 133 MHz PCI Bridge. The high-speed clocking required when designing with the 31154 requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid the designer with board layout. Several factors influence the signal integrity of a 31154 design, including the following:

•Power distribution

•Decoupling

•Minimizing crosstalk

•Layout considerations when routing the PCI-X bus interfaces

The order in which signals are routed varies from designer to designer. Some designers prefer to route all clock signals first, while others prefer to route all high-speed bus signals first. Either order can be used, provided the guidelines listed here are followed.

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Intel manual Routing Guidelines, Intel 31154 133 MHz PCI Bridge Design Guide Design Guide

Contents

April Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide ContentsContents Intel 31154 133 MHz PCI Bridge Design Guide FiguresTables ContentsIntel 31154 133 MHz PCI Bridge Design Guide ContentsDate Revision HistoryContents Intel 31154 133 MHz PCI Bridge Design GuideTerminology and Definition Sheet 1 of About This Document1.1 Terminology and Definitions About This DocumentTerm Table 1. Terminology and Definition Sheet 2 ofAbout This Document Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntroduction PCI-to-PCI Bridge ConfigurationsIntroduction2 2.1 Product OverviewPCI-to-PCI Bridge Architecture Specification, Revision 1.2 compliant 2.2 Features ListFeatures List PCI Local Bus Specification, Revision 2.3 compliantPCI Bus Power Management Interface Specification, Revision 2.3 Related External SpecificationsPCI Local Bus Specification, Revision PCI-to-PCI Bridge Architecture Specification, RevisionIntel 31154 133 MHz PCI Bridge Design Guide Design Guide THIS PAGE INTENTIONALLY LEFT BLANKIntroduction Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationPackage Information BOTTOM VIEW Figure 2. Intel 31154 133 MHz PCI Bridge PackagePackage Information Intel 31154 133 MHz PCI Bridge Design Guide Design GuideAC VSS Figure 3. Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left SidePackage Information Intel 31154 133 MHz PCI Bridge Design Guide Design GuideVCCA Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 13 14 15 16 17 18 19 20Package Information 3.1 Total Signal CountTotal Signal Count SignalsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationTHIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Terminations4Terminations Pull-Up/Pull-Down Terminations Sheet 1 ofTerminations Pull-Up/Pull-Down Terminations Sheet 2 ofSignal Secondary PCI SignalsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Pull-Up/Pull-Down Terminations Sheet 3 ofSignal TerminationsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Pull-Up/Pull-Down Terminations Sheet 4 ofSignal TerminationsTerminations Pull-Up/Pull-Down Terminations Sheet 5 ofSignal resistor defaultIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Pull-Up/Pull-Down Terminations Sheet 6 ofSignal Terminations“Power Sequencing” on page Pull-Up/Pull-Down Terminations Sheet 7 ofSignal “Power Sequencing” on pageIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Pull-Up/Pull-Down Terminations Sheet 8 ofSignal TerminationsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Pull-Up/Pull-Down Terminations Sheet 9 ofSignal TerminationsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide TerminationsTHIS PAGE INTENTIONALLY LEFT BLANK PCI/PCI-X Interface PCI/PCI-X Interface5.1 PCI/PCI-X Voltage Levels 5.2 Interrupt RoutingIDSEL Mapping 5.3 IDSEL Lines5.3.1 Primary IDSEL Line 5.3.2 Secondary IDSEL Lines5.3.4 Secondary Clock Control 5.5 Opaque Memory Region Enable5.3.3 Secondary IDSEL Masking 5.4 CompactPCI* Hot Swap Mode SelectPCI/PCI-X Interface 5.6 PCI-X Initialization Clocking Modes5.6.1 Primary PCI Clocking Mode 5.6.2 Secondary PCI Clocking ModeIntel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Clocking ModesSecondary Bus Frequency Initialization PCI/PCI-X InterfaceIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 5.6.3 Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern PCI/PCI-X InterfaceIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 6.1 CrosstalkFigure 6. Crosstalk Effects on Trace Distance and Height Routing GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 7. PCB Ground Layout Around Connectors6.2 EMI Considerations Routing GuidelinesRouting Guidelines 6.3 Power Distribution and Decoupling6.3.1 Decoupling Recommendations Table 11. Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 6.4 Trace ImpedanceRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Layout GuidelinesPCI-X Layout Guidelines Add-in Card Routing ParametersIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 7.1 PCI Clock Layout GuidelinesPCI-X Layout Guidelines Notes -3%%% ####Intel ####%,%!#%#Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 7.2 PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines PCI-X Layout GuidelinesPCI-X Layout Guidelines Wiring Lengths for 133 MHz Slot7.2.1 Single Slot at 133 MHz Figure 9. Single-Slot Point-to-Point TopologyB3058-01 Wiring Lengths for Embedded 133 MHz DesignPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePCI-X Layout Guidelines Figure 11. Dual-Slot ConfigurationWiring Lengths for 100 MHz Dual-Slot 7.2.2 Dual-Slot at 100 MHzLower AD Bus Wiring Lengths for Embedded 100 MHz DesignPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePCI-X Layout Guidelines Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 1 of7.2.3 Quad-Slots at 66 MHz Figure 13. Quad-Slots 66 MHz TopologyLower AD Bus Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 2 ofPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePCI-X Layout Guidelines Figure 14. Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHzWiring Lengths for Embedded 66 MHz Design 7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHzPCI-X Layout Guidelines 7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview7.2.4 PCI-X at 33 MHz 7.2.4.2 PICMG 1.2 System OverviewIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 15. An Example of an ePCI-X SystemPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Table 20. Wiring Lengths for PICMG 1.2 BackplaneFigure 16. PCI-X Data Bus PICMG 1.2 Style Backplane PCI-X Layout GuidelinesSlotN Table 21. PCI-X Clock Wiring Lengths for PICMG BackplaneFigure 17. PCI-X Clock PICMG 1.2 Style Backplane Slot1Intel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Layout GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Power Considerations8.1 Analog Power Pins Power ConsiderationsIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 8.2 Power SequencingIntel 133 MHz PCI Bridge Power Considerations133 MHz PCI Bridge Figure 21. Intel IQ31154 Customer Reference Board Block DiagramCustomer Reference Board IntelIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Customer Reference Board StackupCustomer Reference Board Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer Connectivity1010.1 Probing PCI-X Signals Debug Connectors and Logic Analyzer ConnectivityIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Logic Analyzer PodDebug Connectors and Logic Analyzer Connectivity Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod AD15 Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityPCI-X Signal Name Logic Analyzer PodIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityThe recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5 from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does not Logic Analyzer PodIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityTHIS PAGE INTENTIONALLY LEFT BLANK Maximum Power Thermal SolutionsThermal Solutions Table 29. Operational PowerIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Thermal SolutionsTHIS PAGE INTENTIONALLY LEFT BLANK Table 30. Design Reference Material References1212.1 Related Documents ReferencesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide ReferencesTHIS PAGE INTENTIONALLY LEFT BLANK