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Intel 31154 manual PCI/PCI-X Interface, 5.1 PCI/PCI-X Voltage Levels, Interrupt Routing

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	PCI/PCI-X Interface
PCI/PCI-X Interface	5

This chapter provides guidelines for designing with the Intel® 31154 133 MHz PCI Bridge PCI/PCI-X bus interface in your application.

5.1PCI/PCI-X Voltage Levels

The Intel® 31154 133 MHz PCI Bridge supports the 5 V PCI signaling interface as well as 3.3 V. Table 6 is provided as a reference for the PCI/PCI-X signaling levels. A complete PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a can be found on the www.pcisig.com website.

Table 6.	PCI/PCI-X Voltage Levels

	Symbol	Parameter	Minimum	Maximum	Units

	VIL3	Input low voltage (PCI-X)	-0.5	0.35 × VCC33	V
	VIH3	Input high voltage (PCI-X/PCI)	0.5 × VCC33	VCC33 + 0.5	V
	VIL4	Input low voltage (PCI)	-0.5	0.3 × VCC33	V
	VOL3	Output low voltage (PCI-X)		0.1 × VCC33	V
	VOH3	Output high voltage (PCI-X)	0.9 × VCC33		V

5.2Interrupt Routing

The 31154 does not use PCI INT lines (INTA, INTB, INTC and INTD). These pins are usually routed from the primary to secondary PCI buses, bypassing the bridge.

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Intel 31154 manual PCI/PCI-X Interface, 5.1 PCI/PCI-X Voltage Levels, Interrupt Routing

Contents

April Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Intel 31154 133 MHz PCI Bridge Design Guide ContentsContents Tables FiguresContents Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide ContentsContents Revision HistoryIntel 31154 133 MHz PCI Bridge Design Guide Date1.1 Terminology and Definitions About This DocumentAbout This Document Terminology and Definition Sheet 1 ofAbout This Document Table 1. Terminology and Definition Sheet 2 ofIntel 31154 133 MHz PCI Bridge Design Guide Design Guide TermIntroduction2 PCI-to-PCI Bridge Configurations2.1 Product Overview IntroductionFeatures List 2.2 Features ListPCI Local Bus Specification, Revision 2.3 compliant PCI-to-PCI Bridge Architecture Specification, Revision 1.2 compliantPCI Local Bus Specification, Revision 2.3 Related External SpecificationsPCI-to-PCI Bridge Architecture Specification, Revision PCI Bus Power Management Interface Specification, RevisionIntel 31154 133 MHz PCI Bridge Design Guide Design Guide THIS PAGE INTENTIONALLY LEFT BLANKIntroduction Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationPackage Information Package Information Figure 2. Intel 31154 133 MHz PCI Bridge PackageIntel 31154 133 MHz PCI Bridge Design Guide Design Guide BOTTOM VIEWPackage Information Figure 3. Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left SideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide AC VSSIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Package Information13 14 15 16 17 18 19 20 VCCATotal Signal Count 3.1 Total Signal CountSignals Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Package InformationTHIS PAGE INTENTIONALLY LEFT BLANK Terminations Terminations4Pull-Up/Pull-Down Terminations Sheet 1 of Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSignal Pull-Up/Pull-Down Terminations Sheet 2 ofSecondary PCI Signals TerminationsSignal Pull-Up/Pull-Down Terminations Sheet 3 ofTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSignal Pull-Up/Pull-Down Terminations Sheet 4 ofTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSignal Pull-Up/Pull-Down Terminations Sheet 5 ofresistor default TerminationsSignal Pull-Up/Pull-Down Terminations Sheet 6 ofTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSignal Pull-Up/Pull-Down Terminations Sheet 7 of“Power Sequencing” on page “Power Sequencing” on pageSignal Pull-Up/Pull-Down Terminations Sheet 8 ofTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSignal Pull-Up/Pull-Down Terminations Sheet 9 ofTerminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide TerminationsTHIS PAGE INTENTIONALLY LEFT BLANK 5.1 PCI/PCI-X Voltage Levels PCI/PCI-X Interface5.2 Interrupt Routing PCI/PCI-X Interface5.3.1 Primary IDSEL Line 5.3 IDSEL Lines5.3.2 Secondary IDSEL Lines IDSEL Mapping5.3.3 Secondary IDSEL Masking 5.5 Opaque Memory Region Enable5.4 CompactPCI* Hot Swap Mode Select 5.3.4 Secondary Clock Control5.6.1 Primary PCI Clocking Mode 5.6 PCI-X Initialization Clocking Modes5.6.2 Secondary PCI Clocking Mode PCI/PCI-X InterfaceSecondary Bus Frequency Initialization PCI-X Clocking ModesPCI/PCI-X Interface Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePCI-X Initialization Pattern 5.6.3 Primary-to-Secondary Frequency LimitsPCI/PCI-X Interface Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesRouting Guidelines Figure 6. Crosstalk Effects on Trace Distance and Height 6.1 CrosstalkRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide6.2 EMI Considerations Figure 7. PCB Ground Layout Around ConnectorsRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide6.3.1 Decoupling Recommendations 6.3 Power Distribution and DecouplingTable 11. Intel 31154 133 MHz PCI Bridge Decoupling Recommendations Routing GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 6.4 Trace ImpedanceRouting Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK PCI-X Layout Guidelines PCI-X Layout GuidelinesAdd-in Card Routing Parameters Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 7.1 PCI Clock Layout GuidelinesPCI-X Layout Guidelines Intel ########%,%!#%# Notes -3%%%PCI-X Slot Guidelines 7.2 PCI-X Topology Layout GuidelinesPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide7.2.1 Single Slot at 133 MHz Wiring Lengths for 133 MHz SlotFigure 9. Single-Slot Point-to-Point Topology PCI-X Layout GuidelinesPCI-X Layout Guidelines Wiring Lengths for Embedded 133 MHz DesignIntel 31154 133 MHz PCI Bridge Design Guide Design Guide B3058-01Wiring Lengths for 100 MHz Dual-Slot Figure 11. Dual-Slot Configuration7.2.2 Dual-Slot at 100 MHz PCI-X Layout GuidelinesPCI-X Layout Guidelines Wiring Lengths for Embedded 100 MHz DesignIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Lower AD Bus7.2.3 Quad-Slots at 66 MHz Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 1 ofFigure 13. Quad-Slots 66 MHz Topology PCI-X Layout GuidelinesPCI-X Layout Guidelines Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 2 ofIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Lower AD BusWiring Lengths for Embedded 66 MHz Design Figure 14. Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz PCI-X Layout Guidelines7.2.4 PCI-X at 33 MHz 7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview7.2.4.2 PICMG 1.2 System Overview PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 15. An Example of an ePCI-X SystemPCI-X Layout Guidelines Figure 16. PCI-X Data Bus PICMG 1.2 Style Backplane Table 20. Wiring Lengths for PICMG 1.2 BackplanePCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideFigure 17. PCI-X Clock PICMG 1.2 Style Backplane Table 21. PCI-X Clock Wiring Lengths for PICMG BackplaneSlot1 SlotNIntel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Layout GuidelinesTHIS PAGE INTENTIONALLY LEFT BLANK 8.1 Analog Power Pins Power ConsiderationsPower Considerations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 133 MHz PCI Bridge 8.2 Power SequencingPower Considerations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideCustomer Reference Board Figure 21. Intel IQ31154 Customer Reference Board Block DiagramIntel 133 MHz PCI BridgeIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Customer Reference Board StackupCustomer Reference Board 10.1 Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Debug Connectors and Logic Analyzer Connectivity Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Logic Analyzer PodDebug Connectors and Logic Analyzer Connectivity Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Logic Analyzer Pod Debug Connectors and Logic Analyzer ConnectivityIntel 31154 133 MHz PCI Bridge Design Guide Design Guide AD15Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod PCI-X Signal Name Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design GuideThe recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5 from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does not Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityTHIS PAGE INTENTIONALLY LEFT BLANK Thermal Solutions Thermal SolutionsTable 29. Operational Power Maximum PowerIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Thermal SolutionsTHIS PAGE INTENTIONALLY LEFT BLANK 12.1 Related Documents References12References Table 30. Design Reference MaterialIntel 31154 133 MHz PCI Bridge Design Guide Design Guide ReferencesTHIS PAGE INTENTIONALLY LEFT BLANK