Intel 31154 manual Figures, Tables

Contents
		7.2.4.2 PICMG 1.2 System Overview	52
8	Power Considerations		57
	8.1	Analog Power Pins	57
	8.2	Power Sequencing	58
9	Customer Reference Board		59
10 Debug Connectors and Logic Analyzer Connectivity			61
	10.1	Probing PCI-X Signals	61
11	Thermal Solutions		69
12	References		71
	12.1	Related Documents	71
Figures
1	Intel® 31154 133 MHz PCI Bridge Applications		9
2	Intel® 31154 133 MHz PCI Bridge Package		14
3	Intel® 31154 133 MHz PCI Bridge Ball Map—Top View, Left Side		15
4	Intel® 31154 133 MHz PCI Bridge Ball Map—Top View, Right Side		16
5	IDSEL Mapping		30
6	Crosstalk Effects on Trace Distance and Height		36
7	PCB Ground Layout Around Connectors		37
8	PCI Clock Distribution and Matching Requirements		43
9	Single-SlotPoint-to-Point Topology		45
10	Embedded Intel® 31154 133 MHz PCI Bridge Design 133 MHz PCI-X Layout		46
11	Dual-Slot Configuration		47
12	Embedded Intel® 31154 133 MHz PCI Bridge Design 100 MHz PCI-X Layout		48
13	Quad-Slots 66 MHz Topology		49
14	Embedded Intel® 31154 133 MHz PCI Bridge Wiring for 66 MHz		51
15	An Example of an ePCI-X System		53
16	PCI-X Data Bus PICMG 1.2 Style Backplane		54
17	PCI-X Clock PICMG 1.2 Style Backplane		55
18	P_VCCA Filter		57
19	S_VCCA Filter		57
20	PVIO Voltage Protection Diode		58
21	Intel® IQ31154 Customer Reference Board Block Diagram		59
Tables
1	Terminology and Definition		7
2	PCI-to-PCI Bridge Configurations		9
3	Features List		10
4	Total Signal Count		17
5	Pull-Up/Pull-Down Terminations		19
6	PCI/PCI-X Voltage Levels		29
7	HS_FREQ Encoding		31
8	PCI-X Clocking Modes		33

4 Intel® 31154 133 MHz PCI Bridge Design Guide