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Total Signal Count
Power Considerations
Thermal Solutions
Features List
Sarbdisable
Primary PCI Clocking Mode
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PCI-X
Layout Guidelines
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Intel
®
31154 133 MHz PCI Bridge Design Guide Design Guide
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Contents
Intel 31154 133 MHz PCI Bridge Design Guide
Design Guide
Intel 31154 133 MHz PCI Bridge Design Guide
Contents
Figures
Tables
Contents
001 Initial release
Revision History
Date Revision Description
About This Document
Terminology and Definitions
Terminology and Definition Sheet 1
Definition
Terminology and Definition Sheet 2
Term
ISI
SHB
PCI-to-PCI Bridge Configurations
Introduction2
Product Overview
Intel 31154 133 MHz PCI Bridge Applications
Features List
Features List
Related External Specifications
References
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Package Information
Intel 31154 133 MHz PCI Bridge Package
Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side
Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side
Total Signal Count
Total Signal Count
Interface Signals
Jtag
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Terminations4
Pull-Up/Pull-Down Terminations Sheet 1
Secondary PCI Signals
Pull-Up/Pull-Down Terminations Sheet 2
Pull-Up/Pull-Down Terminations Sheet 3
PCI Clocks
Pull-Up/Pull-Down Terminations Sheet 4
Hot Swap
Sarbdisable
Pull-Up/Pull-Down Terminations Sheet 5
Hardware Straps sampled at the edge of PRST#
Sarblock
Pull-Up/Pull-Down Terminations Sheet 6
Serial Eeprom
Miscellaneous
Pull-Up/Pull-Down Terminations Sheet 7
Voltages
Pull-Up/Pull-Down Terminations Sheet 8
RSTV0
RSRV1/CRSTEN
SM66EN
Pull-Up/Pull-Down Terminations Sheet 9
NTMASK#
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PCI/PCI-X Interface
PCI/PCI-X Voltage Levels
Interrupt Routing
PCI/PCI-X Voltage Levels
Secondary Idsel Lines
Idsel Lines
Primary Idsel Line
CompactPCI* Hot Swap Mode Select
Opaque Memory Region Enable
Secondary Idsel Masking
Secondary Clock Control
PCI-X Initialization Clocking Modes
Primary PCI Clocking Mode
Secondary PCI Clocking Mode
GND
PCI-X Clocking Modes
Secondary Bus Frequency Initialization
Primary-to-Secondary Frequency Limits
PCI-X Initialization Pattern
Clock Frequency
MHz
Routing Guidelines
Crosstalk
Crosstalk Effects on Trace Distance and Height
PCB Ground Layout Around Connectors
EMI Considerations
Power Distribution and Decoupling
Pins Voltage Capacitor Value Number
Decoupling Recommendations
Intel 31154 133 MHz PCI Bridge Decoupling Recommendations
Trace Impedance
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PCI-X Layout Guidelines
Add-in Card Routing Parameters
PCI Clock Layout Guidelines
####
PCI-X Topology Layout Guidelines
PCI-X Slot Guidelines
Wiring Lengths for 133 MHz Slot
Single Slot at 133 MHz
Lower AD Bus Upper AD Bus Segment
Maximum
Wiring Lengths for Embedded 133 MHz Design
Lower AD Bus Upper AD Bus
Wiring Lengths for 100 MHz Dual-Slot
Dual-Slot at 100 MHz
Wiring Lengths for Embedded 100 MHz Design
Wiring Lengths for 66 MHz Quad-Slot Sheet 1
Quad-Slots at 66 MHz
W13
W14
Wiring Lengths for 66 MHz Quad-Slot Sheet 2
Wiring Lengths for Embedded 66 MHz Design
Minimum Length
Embedded PCI-X Specification Picmg 1.2 Overview
PCI-X at 33 MHz
An Example of an ePCI-X System
Wiring Lengths for Picmg 1.2 Backplane
Segment AD Bus Units
PCI-X Clock Wiring Lengths for Picmg Backplane
Clock Point to Point
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Power Considerations
Analog Power Pins
Power Sequencing
Customer Reference Board
Eeprom
Customer Reference Board Stackup
Debug Connectors and Logic Analyzer Connectivity10
Probing PCI-X Signals
Logic Analyzer Pod
Frame
Devsel
Trdy
BE2
Irdy
AD31
PCI-X Signal Name
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Voltage Maximum Power
Thermal Solutions
Operational Power
Thermal Solutions
References12
Related Documents
Design Reference Material
Design Reference Material
References
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