7.2.2Dual-Slot at 100 MHz
Figure 11 shows one of the secondary bridge PCI AD lines branching into two segments with each going through slot connectors to a buffer on an add-in card. Table 16 shows the corresponding wiring lengths to use as a reference. This two-slot design uses a balanced-star topology.
Figure 11. Dual-Slot Configuration
W1 | W11 | W12 |
| W13 |
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| PCI |
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| Connector | PCI Agent 1 |
I/O Buffer | W14 | W15 | W16 | |
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| Slot 1 |
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| W21 | W22 |
| W23 |
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| PCI |
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| Connector | PCI Agent 2 |
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| Slot 2 |
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Table 16. | Wiring Lengths for 100 MHz |
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| Lower AD Bus | Upper AD Bus |
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| Segment |
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| Units |
| Minimum | Maximum | Minimum | Maximum | ||
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| Length | Length | Length | Length |
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| W1 | 3.5 | 6 | 3.5 | 6 | inches |
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| W21 | 2.0 | 4.5 | 1.0 | 3.5 | inches |
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| W11+W12 | 0.5 | 0.5 | 0.5 | 0.5 | inches |
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| W13 | 0.75 | 1.5 | 1.75 | 2.75 | inches |
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| W14 | 0.1 | 0.1 | N/A | N/A | inches |
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| W15 | 0.6 | 0.6 | N/A | N/A | inches |
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| W16 | 1.125 | 1.125 | N/A | N/A | inches |
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| W21 | 2.0 | 4.5 | 1.0 | 3.5 | inches |
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| W22 | 0.5 | 0.5 | 0.5 | 0.5 | inches |
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| WW23 | 0.75 | 1.5 | 1.75 | 2.75 | inches |
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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide | 47 |
