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Intel 31154 manual PCI Clock Layout Guidelines, PCI-X Layout Guidelines

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PCI-X Layout Guidelines

7.1PCI Clock Layout Guidelines

The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of 0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz, and 133 MHz.

•Total length of P_CLK for an add-in card is 2.4"–2.6"

•Total length of P_CLK in non-add-in card design is less than 8".

Atypical PCI-X application requires separate clock point-to-point connections distributed to each PCI device. The 31154 clock buffer also provides secondary clock fanout of up to nine PCI-X devices. Figure 8, “PCI Clock Distribution and Matching Requirements” on page 43 shows the use of eight secondary clocks going to individual PCI-X devices with S_BRGCLKO fed back into S_CLKIN. The recommended clock buffer layout is specified as follows (refer to Figure 8):

1.The distance between each series resistor and S_CLKO# output clock buffer must be less than 0.5".

2.The segment length from secondary output clock buffer S_CLKO# to the end of the series resistor must be matched less than 0.1".

3.You must match the end of series resistor to the device clock input to less than 0.1" to help keep the timing within the 0.5 ns maximum budget.

4.You must match the length of S_BRGCLKO to the series resistor to less than 0.1" to all the other resistor secondary clock segment lengths listed in item 2, above.

5.Match the length of the other end of the series resistor to S_CLKIN to all the other secondary clock segments lengths labelled in Figure 8 on page 43 as segment length “b”.

6.Keep the distance between the clock lines and other signals (“d”) at least 25 mils from each other.

7.When using a serpentine clock layout, keep the distance between different segments of the same clock line a minimum of 25 mils apart.

8.When there are PCI devices and PCI slots in the design, an extra 2.5" trace length from connector to PCI device must be considered in calculating clock lengths going to PCI slots.

9.When there are PCI slots in the design, S_BRGCLKO must be 3" longer to compensate for the 2.5" trace length from connector to PCI device (and 0.5" for the connector skew) on a PCI add-in card.

42	Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Intel PCI Clock Layout Guidelines, PCI-X Layout Guidelines, Intel 31154 133 MHz PCI Bridge Design Guide Design Guide

Contents

Design Guide Intel 31154 133 MHz PCI Bridge Design GuideApril Intel 31154 133 MHz PCI Bridge Design Guide Contents ContentsIntel 31154 133 MHz PCI Bridge Design Guide Contents FiguresTables Intel 31154 133 MHz PCI Bridge Design GuideContents Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Revision HistoryContents DateAbout This Document About This Document1.1 Terminology and Definitions Terminology and Definition Sheet 1 ofIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Table 1. Terminology and Definition Sheet 2 ofAbout This Document Term2.1 Product Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 IntroductionPCI Local Bus Specification, Revision 2.3 compliant 2.2 Features ListFeatures List PCI-to-PCI Bridge Architecture Specification, Revision 1.2 compliantPCI-to-PCI Bridge Architecture Specification, Revision 2.3 Related External SpecificationsPCI Local Bus Specification, Revision PCI Bus Power Management Interface Specification, RevisionTHIS PAGE INTENTIONALLY LEFT BLANK IntroductionIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Package Information Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 2. Intel 31154 133 MHz PCI Bridge PackagePackage Information BOTTOM VIEWIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 3. Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left SidePackage Information AC VSS13 14 15 16 17 18 19 20 Package InformationIntel 31154 133 MHz PCI Bridge Design Guide Design Guide VCCASignals 3.1 Total Signal CountTotal Signal Count Package InformationPackage Information THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Pull-Up/Pull-Down Terminations Sheet 1 of Terminations4Terminations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSecondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2 ofSignal TerminationsTerminations Pull-Up/Pull-Down Terminations Sheet 3 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTerminations Pull-Up/Pull-Down Terminations Sheet 4 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design Guideresistor default Pull-Up/Pull-Down Terminations Sheet 5 ofSignal TerminationsTerminations Pull-Up/Pull-Down Terminations Sheet 6 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design Guide“Power Sequencing” on page Pull-Up/Pull-Down Terminations Sheet 7 ofSignal “Power Sequencing” on pageTerminations Pull-Up/Pull-Down Terminations Sheet 8 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTerminations Pull-Up/Pull-Down Terminations Sheet 9 ofSignal Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTerminations THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide 5.2 Interrupt Routing PCI/PCI-X Interface5.1 PCI/PCI-X Voltage Levels PCI/PCI-X Interface5.3.2 Secondary IDSEL Lines 5.3 IDSEL Lines5.3.1 Primary IDSEL Line IDSEL Mapping5.4 CompactPCI* Hot Swap Mode Select 5.5 Opaque Memory Region Enable5.3.3 Secondary IDSEL Masking 5.3.4 Secondary Clock Control5.6.2 Secondary PCI Clocking Mode 5.6 PCI-X Initialization Clocking Modes5.6.1 Primary PCI Clocking Mode PCI/PCI-X InterfacePCI/PCI-X Interface PCI-X Clocking ModesSecondary Bus Frequency Initialization Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePCI/PCI-X Interface 5.6.3 Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern Intel 31154 133 MHz PCI Bridge Design Guide Design GuideRouting Guidelines Routing GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing Guidelines 6.1 CrosstalkFigure 6. Crosstalk Effects on Trace Distance and Height Intel 31154 133 MHz PCI Bridge Design Guide Design GuideRouting Guidelines Figure 7. PCB Ground Layout Around Connectors6.2 EMI Considerations Intel 31154 133 MHz PCI Bridge Design Guide Design GuideTable 11. Intel 31154 133 MHz PCI Bridge Decoupling Recommendations 6.3 Power Distribution and Decoupling6.3.1 Decoupling Recommendations Routing Guidelines6.4 Trace Impedance Routing GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Routing Guidelines THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI-X Layout Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design Guide7.1 PCI Clock Layout Guidelines PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide ####%,%!#%# ####Intel Notes -3%%%PCI-X Layout Guidelines 7.2 PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Intel 31154 133 MHz PCI Bridge Design Guide Design GuideFigure 9. Single-Slot Point-to-Point Topology Wiring Lengths for 133 MHz Slot7.2.1 Single Slot at 133 MHz PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Wiring Lengths for Embedded 133 MHz DesignPCI-X Layout Guidelines B3058-017.2.2 Dual-Slot at 100 MHz Figure 11. Dual-Slot ConfigurationWiring Lengths for 100 MHz Dual-Slot PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Wiring Lengths for Embedded 100 MHz DesignPCI-X Layout Guidelines Lower AD BusFigure 13. Quad-Slots 66 MHz Topology Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 1 of7.2.3 Quad-Slots at 66 MHz PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Table 18. Wiring Lengths for 66 MHz Quad-Slot Sheet 2 ofPCI-X Layout Guidelines Lower AD Bus7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz Figure 14. Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHzWiring Lengths for Embedded 66 MHz Design PCI-X Layout Guidelines7.2.4.2 PICMG 1.2 System Overview 7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview7.2.4 PCI-X at 33 MHz PCI-X Layout GuidelinesFigure 15. An Example of an ePCI-X System PCI-X Layout GuidelinesIntel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI-X Layout Guidelines Table 20. Wiring Lengths for PICMG 1.2 BackplaneFigure 16. PCI-X Data Bus PICMG 1.2 Style Backplane Intel 31154 133 MHz PCI Bridge Design Guide Design GuideSlot1 Table 21. PCI-X Clock Wiring Lengths for PICMG BackplaneFigure 17. PCI-X Clock PICMG 1.2 Style Backplane SlotNPCI-X Layout Guidelines THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Power Considerations Power Considerations8.1 Analog Power Pins Intel 31154 133 MHz PCI Bridge Design Guide Design GuidePower Considerations 8.2 Power SequencingIntel 133 MHz PCI Bridge Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel Figure 21. Intel IQ31154 Customer Reference Board Block DiagramCustomer Reference Board 133 MHz PCI BridgeCustomer Reference Board Stackup Customer Reference BoardIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer Connectivity Debug Connectors and Logic Analyzer Connectivity1010.1 Probing PCI-X Signals Intel 31154 133 MHz PCI Bridge Design Guide Design GuideLogic Analyzer Pod Debug Connectors and Logic Analyzer ConnectivityIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer Connectivity Logic Analyzer PodIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Debug Connectors and Logic Analyzer ConnectivityLogic Analyzer Pod AD15Debug Connectors and Logic Analyzer Connectivity Logic Analyzer PodIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Logic Analyzer Pod Debug Connectors and Logic Analyzer ConnectivityPCI-X Signal Name Intel 31154 133 MHz PCI Bridge Design Guide Design GuideLogic Analyzer Pod Debug Connectors and Logic Analyzer ConnectivityThe recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5 from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does not Intel 31154 133 MHz PCI Bridge Design Guide Design GuideDebug Connectors and Logic Analyzer Connectivity THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide Table 29. Operational Power Thermal SolutionsThermal Solutions Maximum PowerThermal Solutions THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide References References1212.1 Related Documents Table 30. Design Reference MaterialReferences THIS PAGE INTENTIONALLY LEFT BLANKIntel 31154 133 MHz PCI Bridge Design Guide Design Guide