Intel 31154 manual PCI Clock Layout Guidelines

PCI-X Layout Guidelines

7.1PCI Clock Layout Guidelines

The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of 0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz, and 133 MHz.

•Total length of P_CLK for an add-in card is 2.4"–2.6"

•Total length of P_CLK in non-add-in card design is less than 8".

Atypical PCI-X application requires separate clock point-to-point connections distributed to each PCI device. The 31154 clock buffer also provides secondary clock fanout of up to nine PCI-X devices. Figure 8, “PCI Clock Distribution and Matching Requirements” on page 43 shows the use of eight secondary clocks going to individual PCI-X devices with S_BRGCLKO fed back into S_CLKIN. The recommended clock buffer layout is specified as follows (refer to Figure 8):

1.The distance between each series resistor and S_CLKO# output clock buffer must be less than 0.5".

2.The segment length from secondary output clock buffer S_CLKO# to the end of the series resistor must be matched less than 0.1".

3.You must match the end of series resistor to the device clock input to less than 0.1" to help keep the timing within the 0.5 ns maximum budget.

4.You must match the length of S_BRGCLKO to the series resistor to less than 0.1" to all the other resistor secondary clock segment lengths listed in item 2, above.

5.Match the length of the other end of the series resistor to S_CLKIN to all the other secondary clock segments lengths labelled in Figure 8 on page 43 as segment length “b”.

6.Keep the distance between the clock lines and other signals (“d”) at least 25 mils from each other.

7.When using a serpentine clock layout, keep the distance between different segments of the same clock line a minimum of 25 mils apart.

8.When there are PCI devices and PCI slots in the design, an extra 2.5" trace length from connector to PCI device must be considered in calculating clock lengths going to PCI slots.

9.When there are PCI slots in the design, S_BRGCLKO must be 3" longer to compensate for the 2.5" trace length from connector to PCI device (and 0.5" for the connector skew) on a PCI add-in card.

42 Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide