Revision History, Date Revision Description | Intel 31154 instruction

Contents

Revision History

Date	Revision	Description

April 2004	001	Initial release

6	Intel® 31154 133 MHz PCI Bridge Design Guide

Image 6

Intel 31154 manual Revision History, Date Revision Description, Initial release

Contents

Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Intel 31154 133 MHz PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description001 Initial release Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions Definition ISI Terminology and Definition Sheet 2Term SHB Product Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge Applications Features List Features List Related External Specifications References This page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count Jtag This page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1 Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2 Pull-Up/Pull-Down Terminations Sheet 3 PCI Clocks Pull-Up/Pull-Down Terminations Sheet 4 Hot Swap Hardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 Sarblock Pull-Up/Pull-Down Terminations Sheet 6 Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66EN Pull-Up/Pull-Down Terminations Sheet 9 NTMASK# This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage Levels Idsel Lines Primary Idsel LineSecondary Idsel Lines Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock Control Primary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHz Routing Guidelines Crosstalk Crosstalk Effects on Trace Distance and Height PCB Ground Layout Around Connectors EMI Considerations Decoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling Recommendations Trace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing Parameters PCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot Guidelines Lower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz Maximum Wiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD Bus Wiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHz Wiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum Length Embedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHz An Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus Units PCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to Point This page Intentionally Left Blank Power Considerations Analog Power Pins Power Sequencing Customer Reference Board Eeprom Customer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X Signals Logic Analyzer Pod Trdy FrameDevsel BE2 Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference Material References