Datasheet
Intel 82854 Graphics Memory Controller Hub Gmch
D15343-003
Contents
Intel 82854 Graphics Memory Controller Hub Gmch
10.9
127
Figures
152
Revision History
Date Revision Description
Intel 82854 Graphics Memory Controller Hub Gmch
Memory System
Overview
Processor/Host Bus Support
Video Overlay
System Interrupts
Video Stream Decoder
Internal Graphics Features
Display
Intel 82854 Graphics Memory Controller Hub Gmch
Hub Interface to ICH4-M
Graphic Power Management
Power Management
Intel 854 Chipset system block diagram Native Graphic mode
Package
Term Description
Terminology
Terms and Descriptions
ICH4-M
Document Location
Reference Documents
Reference Documents
Intel 82854 Graphics Memory Controller Hub Gmch
System Architecture
Intel 82854 Gmch
Processor Host Interface
Gmch System Memory Interface
DDR Sdram Memory Capacity
Technology Width
Graphics Features
Display Features
Gmch Analog Display Port
Gmch Integrated DVO Ports
Hub Interface
Address Decode Policies
Gmch Clocking
Intel 82854 Gmch Interface Clocks
Ratio
Bytes MB/s
System Interrupts
Notation Description
Buffer Description
Host Interface Signals
Host Interface Signal Descriptions
DRDY#
HIT#
HITM#
HLOCK#
RS20#
RS20# Response type
DDR Sdram Interface
DDR Sdram Interface Descriptions
SRAS#
SCAS#
Hub Interface Signals
Hub Interface Signals
Clocks
Display Power Management Signaling This signal is used only
Dpms
DAC Clocking
Drefclk
Digital Video Output B Dvob Port
Internal Graphics Display Signals
Digital Video Output B Dvob Port Signal Descriptions
Digital Video Output C Dvoc Port Signal Descriptions
Digital Video Output C Dvoc Port
Analog CRT Display
Dvob and Dvoc Port Common Signal Descriptions
Analog CRT Display Signal Descriptions
General Purpose Input/Output Signals
Gpio Signal Descriptions
Voltage References, PLL Power
Voltage References, PLL Power
Hlrcomp
Pswing
Hlvref
Vcchl
Gmch Function Bus #0, Device#
Conceptual Overview of the Platform Configuration Structure
Device Number Assignment
Nomenclature for Access Attributes
Nomenclature for Access Attributes
PCI Bus #0 Configuration Mechanism
Standard PCI Bus Configuration Mechanism
Routing Configuration Accesses
Primary PCI and Downstream Configuration Mechanism
Default Value upon Reset
Register Definitions
Reserved Bits
Configaddress Configuration Address Register
I/O Mapped Registers
Bit Descriptions
Reserved
Configdata Configuration Data Register
Configuration Data Register
VGA I/O Mapped Registers
VGA I/O Mapped Register List
Index Data Registers
Name Function Read @ Write @
End
Gmch Configuration Space Device #0, Function#0
Register Name Default Value Access
Attbase
Bit Descriptions 150
VID Vendor Identification Register
Did Device Identification Register
Pcicmd PCI Command Register
= Serr message is not generated by the Gmch for Device #0
PCI Status Register
RID Register Identification
Subc Sub Class Code Register
Svid Subsystem Vendor Identification Register
BCC Base Class Code Register
HDR Header Type Register
SID Subsystem Identification Register
Capptr Capabilities Pointer Register
Capid Capabilities Identification Register Device #0
Capability ID
Rrbar Access Enable-R/W
GMC Gmch Miscellaneous Control Register Device #0
MDA Present MDAP-R/W
VGA
Bit
Reserved Device #2 Function #1 Enable/Disable
GGC Gmch Graphics Control Register Device #0
Bit Description
Dafc Device and Function Control Register Device #0
Fdhc Fixed Dram Hold Control Register Device #0
Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved
17 PAM60 Programmable Attribute Map Register Device #0
Attribute Bit Assignment
PAM Registers
PAM Registers and Associated System Memory Segments
DOS Application Area 00000h-9FFFh
Video Buffer Area A0000h-BFFFFh
Expansion Area C0000h-DFFFFh
Smram System Management RAM Control Register Device #0
Extended System Bios Area E0000h-EFFFFh
System Bios Area F0000h-FFFFFh
Esmramc Extended System Management RAM Control Device #0
Errsts Error Status Register Device #0
Errcmd Error Command Register Device #0
Smicmd SMI Error Command Register Device #0
Bit Description Reserved
Scicmd SCI Error Command Register Device #0
Reserved SCI on Multiple-bit ECC Error
SCI on Single-bit ECC Error
SCI on Gmch Thermal Sensor Trip
Reserved On Die Termination ODT Gating Disable
Reserved FSB Data Bus Power Management Control
C2 state Gmch FSB Interface Power Management Control
Shic Secondary Host Interface Control Register Device #0
HEM Host Error Control, Status, and Observation Device #0
DRB
VID Vendor Identification Register
Pcicmd PCI Command Register
Pcists PCI Status Register
RID Revision Identification Register
Device. Reads and Writes to this location have no effect
DRB Dram Row 03 Boundary Register Device #0
DRA Dram Row Attribute Register Device #0
DDR Internal Write to Read Command delay tWTR
DDR Write Recovery time tWR
DRT Dram Timing Register Device #0
Examples of usage
Encoding CK between RD and WR commands
Back To Back Read-Read commands spacing DDR, different Rows
Encoding CK between RD and RD commands
Refresh Cycle Time tRFC
Reserved CAS# Latency tCL
Activate to Precharge delay tRAS, MAX
Activate to Precharge delay tRAS, MIN
PCEn Page Close Enable TC Timer Control PDEn23
CS# Signal Drive Control
Dynamic Memory Interface Power Management
Rcven DLL shutdown disable
Power State S1/S3 Refresh Control
DRC Dram Controller Mode Register Device #0
Ddim DDR Sdram Data Integrity Mode
000
001
010
011
For Double Data Rate
DTC Dram Throttling Control Register Device #0
DDR Sdram Throttle Mode Tmode
Wttc
2724
Thermal Power Throttle Control fields Enable
High Priority Stream Throttling Enable
Hpllcc
Did Device Identification Register
Pcicmd PCI Command Register
Pcists PCI Status Register
Subc Sub-Class Code Register
ID Subsystem Identification Register
Hpllcc Hpll Clock Control Register Device #0
Hpll VCO Change Sequence Initiate Bit
Straps Read GFX Core
HPLLCC20
DVO Port CRT Port
Rate
Register Name
Regs
VID Vendor Identification Register Device #2
Did Device Identification Register Device #2
Pcicmd PCI Command Register Device #2
Pcists PCI Status Register Device #2
RID Revision Identification Register Device #2
MLT Master Latency Timer Register Device #2
CC Class Code Register Device #2
CLS Cache Line Size Register Device #2
Base Class Code Basec 03=Display controller
Bit Description Master Latency Timer Count Value RO
Prefetchable Memory-RO Enable prefetching
HDR Header Type Register Device #2
Gmadr Graphics Memory Range Address Register Device #2
Mmadr Memory Mapped Range Address Register Device #2
Iobar I/O Base Address Register Device #2
Prefetchable Memory-RO Prevents prefetching
Memory / IO Space-RO
SID Subsystem Identification Register Device #2
Romadr Video Bios ROM Base Address Registers Device #2
Svid Subsystem Vendor Identification Register Device #2
Mingnt Minimum Grant Register Device #2
Intrline Interrupt Line Register Device #2
Intrpin Interrupt Pin Register Device #2
Maxlat Maximum Latency Register Device #2
Pmcap Power Management Capabilities Register Device #2
Auxiliary Power Source Hardwired to
Pmcs Power Management Control/Status Register Device #2
Bits10 Power State
System Memory Address Ranges
Simplified View of System Address Map
DOS Compatibility Area
Detailed View of System Address Map
System Memory Segments and Their Attributes
DOS Area 000000h-09FFFFh
Legacy VGA Ranges 0A0000h-0BFFFFh
Compatible Smram Address Range 0A0000h-0BFFFFh
Extended System Bios Area 0E0000h-0EFFFFh
System Bios Area 0F0000h-0FFFFFh
Extended System Memory Area
Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh
1 15 MB-16 MB Window
Pre-allocated System Memory
Pre-allocated System Memory
Attributes Comments
Extended Smram Address Range Hseg and Tseg
Hseg
Tseg
Dynamic Video Memory Technology Dvmt
High Bios Area FFE00000h -FFFFFFFFh
PCI Memory Address Range Top of Main System Memory to 4 GB
SMM Space Definition
System Management Mode SMM Memory Range
SMM Space Restrictions
SMM Space Transaction Handling
System Memory Shadowing
5 I/O Address Space
Gmch Decode Rules and Cross-Bridge Address Mapping
PCI I/O Address Mapping
Hub Interface Accesses to Gmch that Cross Device Boundaries
Hub Interface Decode Rules
Interface Decode Rules
Cycles Initiated Using PCI Protocol
Accesses to Gmch that Cross Device Boundaries
Host Interface Overview
Dynamic Bus Inversion
System Bus Interrupt Delivery
Relation of DBI Bits to Data Bits
System Memory Organization and Configuration
Configuration Mechanism for DDR DIMMs
System Memory Interface
Upstream Interrupt Messages
DDR Sdram Performance Description
System Memory Register Programming
Data Bytes on DDR Dimm Used for Programming Dram Registers
Byte Function
Integrated Graphics Overview
1 3D/2D Instruction Processing
Setup Engine
2 3D Engine
Viewport Transform and Perspective Divide
2.3 3D Primitives and Data Formats Support
Backface Culling
Scan Converter
Texture Engine
Perspective Correct Texture Support
Texture Map Filtering
Texture Chromakey
Anti-Aliasing
Raster Engine
Multiple Texture Composition
Cubic Environment Mapping
Bump Mapping
Texture Map Blending
Combining Intrinsic and Specular Color Components
Color Shading Modes
Color Dithering
Depth Buffer
Alpha Blending
Color Buffer Formats Destination Alpha
4 2D Engine
Stencil Buffer
Projective Textures
4.1 256-Bit Pattern Fill and BLT Engine
Hardware Cursor Plane Native Graphic Mode only
Dual Display Usage Model Native Graphic Mode only
Planes and Engines
Alpha Stretch BLT
Overlay Plane
Color Control
Dynamic Bob and Weave
Video Functionality
MPEG-2 Decoding
Hardware Motion Compensation
Sub-picture Support
Internal Graphic Display Interface
Pipe a Timing Generator Unit
1.2 H, V timing signals for active and blank timing
Arib Support
Parameters
HSYNC/VSYNC Field Timing
Interlace support for Plane a graphics
Blend Function
Interlaced Video Field display
Arib 960 X 540 support
Interlace support for Video Overlay Window
DVO Control Data Bits
Timing Register Switching
DDC Display Data Channel
Analog Display Port Characteristics
Integrated Ramdac
146 D15343-003
Power and Thermal Management
General Description of Supported CPU States
General Description of Acpi States
Hysteresis Operation
Internal Thermal Sensor
Overview
External Thermal Sensor Input
Usage
Pin Name Strap Description Configuration Type Buffer Type
Strapping Configuration
Strapping Signals and Configuration
FSB Freq DDR Freq Gfx Freq Core Vcc
Intel 82854 Gmch Straps for Frequency/CPU Configuration
GST20
Ballout and Package Information
Name Voltage Level Ball out
VCC/VSS Voltage Groups
Voltage Levels and Ball Out for Voltage Groups
Row Column Signal Name
Ballout Table
156 D15343-003
D15343-003 157
158 D15343-003
D15343-003 159
160 D15343-003
D15343-003 161
162 D15343-003
D15343-003 163
Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View
Package Mechanical Information
Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View
Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View