Intel D15343-003 manual Timing Register Switching

Intel® 82854 Graphics Memory Controller Hub (GMCH)

Figure 11 shows how the timing registers switch while the buffer 0 and buffer 1 are scanned out.

Figure 11. Timing Register Switching

			HTOTAL A	HSYNC A	HBLANK A
					VSYNC_A
					VBLANK_A
Buffer 0					VTOTAL_A
MP@ML 720x480(i) / 720x480(p)
					timing register switching
		VSYNC_B			occurs on VBLANK rising edge
Buffer 1		VBLANK_B
		VTOTAL_B
		VBLANK
		VTOTAL	04650438h			062705A0h
		VTOTAL_A			04650438h
		VTOTAL_B			062705A0h
HTOTAL B	HSYNC B	HBLANK B

As shown in the above figure, buffer switching in Multi-display mode occurs on VBLANK. Once VBLANK is detected, horizontal and vertical counters are reset and register switching occurs. These operations result in an extended HSYNC following the VBLANK. The HSYNC interval following VBLANK rising edge in MTV mode can be calculated as follows:

When switching from Buffer0 to Buffer1:

HSYNC INTERVAL = HSYNC_B[27:16] + 8

When switching from Buffer1 to Buffer0:

HSYNC INTERVAL = HSYNC_A[27:16] + 8

Where HSYNC_A[27:16] and HSYNC_B[27:16] are the Horizontal Sync End values programmed in the PipeA and PipeB Horizontal Sync Registers.

In addition, VBLANK is effectively started twice as a result of the counter reset. This results in two lines of inactive data being repeated. VSYNC will start two lines later then the programmed value, and the total number of lines is extended by two.

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