Manuals / Intel / Computer Equipment / Switch

Intel D15343-003 manual HEM Host Error Control, Status, and Observation Device #0, Bit Description

Models: D15343-003

1 166

Download 166 pages 1.01 Kb

Page 71

Register Description

4.8.25HEM – Host Error Control, Status, and Observation (Device #0)

Address Offset:			F0-F3h
Default Value:			00000000h
Access:			Read Only, Read/Write
Size:			32 bits

	Bit	Description

	31	Detected HADSTB1# Glitch (ASTB1GL): This bit is set when the GMCH has detected a glitch
		on address strobe HADSTB1#. Software must write a 1 to clear this status bit.

	30	Detected HADSTB0# Glitch (ASTB0GL): This bit is set when the GMCH has detected a glitch
		on address strobe HADSTB0#. Software must write a 1 to clear this status bit.

	29	Detected HDSTB3# Glitch (DSTB3GL): This bit is set when the GMCH has detected a glitch on
		data strobe pair HDSTB3#. Software must write a 1 to clear this status bit.

	28	Detected HDSTB2# Glitch (DSTB2GL): This bit is set when the GMCH has detected a glitch on
		data strobe pair HDSTB2#. Software must write a 1 to clear this status bit.

	27	Detected HDSTB1# Glitch (DSTB1GL): This bit is set when the GMCH has detected a glitch on
		data strobe pair HDSTB1#. Software must write a 1 to clear this status bit.

D15343-003

71

Image 71

Intel D15343-003 manual HEM Host Error Control, Status, and Observation Device #0, Bit Description

Contents

Intel 82854 Graphics Memory Controller Hub Gmch DatasheetD15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Date Revision Description Revision HistoryIntel 82854 Graphics Memory Controller Hub Gmch Memory System OverviewProcessor/Host Bus Support Video Overlay System InterruptsVideo Stream Decoder Display Internal Graphics FeaturesIntel 82854 Graphics Memory Controller Hub Gmch Hub Interface to ICH4-M Graphic Power ManagementPower Management Package Intel 854 Chipset system block diagram Native Graphic modeTerm Description TerminologyTerms and Descriptions ICH4-M Document Location Reference DocumentsReference Documents Intel 82854 Graphics Memory Controller Hub Gmch Intel 82854 Gmch System ArchitectureTechnology Width Processor Host InterfaceGmch System Memory Interface DDR Sdram Memory CapacityGmch Integrated DVO Ports Graphics FeaturesDisplay Features Gmch Analog Display PortAddress Decode Policies Hub InterfaceBytes MB/s Gmch ClockingIntel 82854 Gmch Interface Clocks RatioSystem Interrupts Buffer Description Notation DescriptionHost Interface Signal Descriptions Host Interface SignalsHLOCK# DRDY#HIT# HITM#RS20# Response type RS20#SCAS# DDR Sdram InterfaceDDR Sdram Interface Descriptions SRAS#Hub Interface Signals Hub Interface SignalsClocks Drefclk Display Power Management Signaling This signal is used onlyDpms DAC ClockingDigital Video Output B Dvob Port Internal Graphics Display SignalsDigital Video Output B Dvob Port Signal Descriptions Digital Video Output C Dvoc Port Digital Video Output C Dvoc Port Signal DescriptionsAnalog CRT Display Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Signal Descriptions Gpio Signal Descriptions General Purpose Input/Output SignalsVoltage References, PLL Power Voltage References, PLL PowerVcchl HlrcompPswing HlvrefGmch Function Bus #0, Device# Conceptual Overview of the Platform Configuration StructureDevice Number Assignment Nomenclature for Access Attributes Nomenclature for Access AttributesPCI Bus #0 Configuration Mechanism Standard PCI Bus Configuration MechanismRouting Configuration Accesses Reserved Bits Primary PCI and Downstream Configuration MechanismDefault Value upon Reset Register DefinitionsI/O Mapped Registers Configaddress Configuration Address RegisterReserved Bit DescriptionsConfiguration Data Register Configdata Configuration Data RegisterName Function Read @ Write @ VGA I/O Mapped RegistersVGA I/O Mapped Register List Index Data RegistersEnd Gmch Configuration Space Device #0, Function#0Register Name Default Value Access Attbase Bit Descriptions 150 VID Vendor Identification RegisterDid Device Identification Register = Serr message is not generated by the Gmch for Device #0 Pcicmd PCI Command RegisterPCI Status Register Subc Sub Class Code Register RID Register IdentificationSvid Subsystem Vendor Identification Register BCC Base Class Code RegisterHDR Header Type Register Capptr Capabilities Pointer Register SID Subsystem Identification RegisterCapability ID Capid Capabilities Identification Register Device #0VGA Rrbar Access Enable-R/WGMC Gmch Miscellaneous Control Register Device #0 MDA Present MDAP-R/WBit Reserved Device #2 Function #1 Enable/DisableGGC Gmch Graphics Control Register Device #0 Bit Description Dafc Device and Function Control Register Device #0Fdhc Fixed Dram Hold Control Register Device #0 Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved 17 PAM60 Programmable Attribute Map Register Device #0Attribute Bit Assignment PAM Registers Expansion Area C0000h-DFFFFh PAM Registers and Associated System Memory SegmentsDOS Application Area 00000h-9FFFh Video Buffer Area A0000h-BFFFFhSmram System Management RAM Control Register Device #0 Extended System Bios Area E0000h-EFFFFhSystem Bios Area F0000h-FFFFFh Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Bit Description Reserved Smicmd SMI Error Command Register Device #0SCI on Gmch Thermal Sensor Trip Scicmd SCI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error SCI on Single-bit ECC ErrorShic Secondary Host Interface Control Register Device #0 Reserved On Die Termination ODT Gating DisableReserved FSB Data Bus Power Management Control C2 state Gmch FSB Interface Power Management ControlHEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 Examples of usage DDR Internal Write to Read Command delay tWTRDDR Write Recovery time tWR DRT Dram Timing Register Device #0Refresh Cycle Time tRFC Encoding CK between RD and WR commandsBack To Back Read-Read commands spacing DDR, different Rows Encoding CK between RD and RD commandsReserved CAS# Latency tCL Activate to Precharge delay tRAS, MAXActivate to Precharge delay tRAS, MIN Rcven DLL shutdown disable PCEn Page Close Enable TC Timer Control PDEn23CS# Signal Drive Control Dynamic Memory Interface Power ManagementPower State S1/S3 Refresh Control Ddim DDR Sdram Data Integrity Mode DRC Dram Controller Mode Register Device #0011 000001 010For Double Data Rate DTC Dram Throttling Control Register Device #0 Wttc DDR Sdram Throttle Mode Tmode2724 High Priority Stream Throttling Enable Thermal Power Throttle Control fields EnableHpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpll VCO Change Sequence Initiate Bit Hpllcc Hpll Clock Control Register Device #0Rate Straps Read GFX CoreHPLLCC20 DVO Port CRT PortRegs Register NameDid Device Identification Register Device #2 VID Vendor Identification Register Device #2Pcicmd PCI Command Register Device #2 RID Revision Identification Register Device #2 Pcists PCI Status Register Device #2Base Class Code Basec 03=Display controller MLT Master Latency Timer Register Device #2CC Class Code Register Device #2 CLS Cache Line Size Register Device #2Gmadr Graphics Memory Range Address Register Device #2 Bit Description Master Latency Timer Count Value ROPrefetchable Memory-RO Enable prefetching HDR Header Type Register Device #2Memory / IO Space-RO Mmadr Memory Mapped Range Address Register Device #2Iobar I/O Base Address Register Device #2 Prefetchable Memory-RO Prevents prefetchingSID Subsystem Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2Svid Subsystem Vendor Identification Register Device #2 Mingnt Minimum Grant Register Device #2 Intrline Interrupt Line Register Device #2Intrpin Interrupt Pin Register Device #2 Maxlat Maximum Latency Register Device #2 Pmcap Power Management Capabilities Register Device #2Auxiliary Power Source Hardwired to Bits10 Power State Pmcs Power Management Control/Status Register Device #2Simplified View of System Address Map System Memory Address RangesDetailed View of System Address Map DOS Compatibility AreaCompatible Smram Address Range 0A0000h-0BFFFFh System Memory Segments and Their AttributesDOS Area 000000h-09FFFFh Legacy VGA Ranges 0A0000h-0BFFFFhMonochrome Display Adapter MDA Range 0B0000h 0B7FFFh Extended System Bios Area 0E0000h-0EFFFFhSystem Bios Area 0F0000h-0FFFFFh Extended System Memory AreaAttributes Comments 1 15 MB-16 MB WindowPre-allocated System Memory Pre-allocated System MemoryDynamic Video Memory Technology Dvmt Extended Smram Address Range Hseg and TsegHseg TsegPCI Memory Address Range Top of Main System Memory to 4 GB High Bios Area FFE00000h -FFFFFFFFhSMM Space Definition System Management Mode SMM Memory RangeSMM Space Restrictions SMM Space Transaction Handling System Memory Shadowing5 I/O Address Space PCI I/O Address Mapping Gmch Decode Rules and Cross-Bridge Address MappingHub Interface Decode Rules Hub Interface Accesses to Gmch that Cross Device BoundariesInterface Decode Rules Cycles Initiated Using PCI ProtocolAccesses to Gmch that Cross Device Boundaries Relation of DBI Bits to Data Bits Host Interface OverviewDynamic Bus Inversion System Bus Interrupt DeliveryUpstream Interrupt Messages System Memory Organization and ConfigurationConfiguration Mechanism for DDR DIMMs System Memory InterfaceByte Function DDR Sdram Performance DescriptionSystem Memory Register Programming Data Bytes on DDR Dimm Used for Programming Dram Registers1 3D/2D Instruction Processing Integrated Graphics Overview2.3 3D Primitives and Data Formats Support Setup Engine2 3D Engine Viewport Transform and Perspective DividePerspective Correct Texture Support Backface CullingScan Converter Texture EngineTexture Map Filtering Texture ChromakeyAnti-Aliasing Bump Mapping Raster EngineMultiple Texture Composition Cubic Environment MappingColor Dithering Texture Map BlendingCombining Intrinsic and Specular Color Components Color Shading ModesDepth Buffer Alpha BlendingColor Buffer Formats Destination Alpha 4.1 256-Bit Pattern Fill and BLT Engine 4 2D EngineStencil Buffer Projective TexturesAlpha Stretch BLT Hardware Cursor Plane Native Graphic Mode onlyDual Display Usage Model Native Graphic Mode only Planes and EnginesOverlay Plane Dynamic Bob and Weave Color ControlSub-picture Support Video FunctionalityMPEG-2 Decoding Hardware Motion CompensationPipe a Timing Generator Unit Internal Graphic Display InterfaceArib Support 1.2 H, V timing signals for active and blank timingHSYNC/VSYNC Field Timing ParametersInterlace support for Plane a graphics Blend FunctionInterlaced Video Field display Arib 960 X 540 support DVO Control Data Bits Interlace support for Video Overlay WindowTiming Register Switching DDC Display Data Channel Analog Display Port CharacteristicsIntegrated Ramdac 146 D15343-003 Power and Thermal Management General Description of Acpi States General Description of Supported CPU StatesHysteresis Operation Internal Thermal SensorOverview Usage External Thermal Sensor InputPin Name Strap Description Configuration Type Buffer Type Strapping ConfigurationStrapping Signals and Configuration FSB Freq DDR Freq Gfx Freq Core Vcc Intel 82854 Gmch Straps for Frequency/CPU ConfigurationGST20 Ballout and Package Information Name Voltage Level Ball out VCC/VSS Voltage GroupsVoltage Levels and Ball Out for Voltage Groups Ballout Table Row Column Signal Name156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Top ViewIntel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View