Intel D15343-003 manual Register Definitions, Primary PCI and Downstream Configuration Mechanism

Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.4.2Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, the GMCH will generate a Type 1 Hub interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1 configuration cycle will be “01”. This Hub interface configuration cycle will be sent over Hub interface.

If the cycle is forwarded to the ICH4-M via Hub interface, the ICH4-M compares the non-zero Bus Number with the Secondary bus number and Subordinate bus number registers of its PCI-to-PCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH4-M’s Hub interfaces, or a downstream PCI bus.

4.5Register Definitions

The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O Address Space, and they are as follows:

•Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.

•Internal Configuration registers: residing within the GMCH, they are partitioned into two logical device register sets (“logical” since they reside within the single physical device). The first register set is dedicated to Host-HI Bridge functionality (that is, DDR SDRAM configuration, other chip-set operating parameters and optional features). The second register block is for the integrated graphics functions.

•Internal Memory Mapped Configuration registers: reside in the GMCH Device #0.

•Internal Memory Mapped Configuration registers, Legacy VGA registers, or blending function registers: reside in the GMCH Device #2 that controls the Integrated Graphics Controller.

The GMCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte numeric fields use “Little Endian Byte Ordering” (that is, lower addresses contain the least significant parts of the field).

Reserved Bits

Some of the GMCH registers described in this section contain Reserved bits. These bits are labeled “Reserved”. Software must deal correctly with fields that are Reserved. On Reads, software must use appropriate Masks to extract the defined bits and not rely on Reserved bits being any particular value. On Writes, software must ensure that the values of Reserved bit positions are preserved.

That is, the values of Reserved bit positions must first be Read, Merged with the new values for other bit positions and then Written back.

Note: The software does not need to perform Read, Merge, and Write operations for the Configuration Address register.

Default Value upon Reset

Upon a Full Reset, the GMCH sets all of its Internal Configuration registers to a predetermined default state. Some register values at Reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the

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