Intel D15343-003 manual Overview, Processor/Host Bus Support, Memory System

Introduction

1.0Introduction

This document is the datasheet for the Intel® 82854 Graphics Memory Controller Hub (GMCH).

1.1Overview

The Intel® 854 chipset is a combination of the Intel® 82854 Graphics Memory Controller Hub (GMCH) (Graphics Memory Controller Hub) and ICH4-M (I/O Controller Hub). The Intel 854 Chipset is designed to work with the Ultra Low Voltage (ULV) Intel® Celeron® M processor at 600 MHz with 512 KB of on-die L2 cache on an 0.13 micron process, Genuine Intel® Processor at 1.2 GHz, and Genuine Intel® Processor at 1.5 GHz. The Intel® 82854 GMCH provides high- performance, integrated graphics and manages the flow of information. Figure 1 depicts the Intel 854 chipset block diagram.

Processor/Host Bus Support

The Genuine Intel® Processor at 1.2 GHz and Genuine Intel® Processor at 1.5 GHz have the following key features:

•High performance, low power core

•AGTL+ bus driver technology with integrated AGTL+ termination resistors and low voltage operation

•Supports Intel Architecture with Dynamic Execution

•400-MHz, Source-Synchronous processor system bus

•2x address, 4x data

•On-die, primary 32-Kbyte instruction cache and 32-Kbyte write-back data cache

•On-die, 512-Kbyte second level cache with Advanced Transfer Cache Architecture

•Advanced Branch Prediction and Data Prefetch Logic

•Streaming SIMD Extensions 2 (SSE2)

•Advanced Power Management features

Memory System

•Directly supports one DDR SDRAM channel, 64-bits wide

•Supports 266/333-MHz DDR SDRAM devices with max of two, double-sided DIMM (four rows populated) with unbuffered PC2100/PC2700 DDR SDRAM.

•Supports 128-Mbit, 256-Mbit, and 512-Mbit technologies providing maximum capacity of 2 GB with x16 devices

•All supported devices have four banks

•Supports up to 16 simultaneous open pages

•Supports page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for every row

•UMA support only

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