Internal Graphic Display Interface | Intel D15343-003 specs

Intel® 82854 Graphics Memory Controller Hub (GMCH)

6.5Internal Graphic Display Interface

The GMCH has three dedicated display ports: an Analog CRT port and two Digital display ports, DVOB and DVOC.

When the GMCH is strapped to operate in Native Graphic Mode, the DVOB and DVOC can support down stream devices such as TV-out encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. The data that is sent out the display ports are selected from one of the two possible sources, display pipe A or display pipe B.

The GMCH's digital display port is capable of driving a 165-MHz pixel clock on a single DVO port, or a 330-MHz pixel clock by combining DVOB and DVOC.

6.5.1Pipe A Timing Generator Unit

The Pipe A Timing generator provides the basic timing information for Display Pipe A. Timings are composed of blank, sync, border and active periods. The active period represents the data area; this is normally the size of a fixed resolution display or the selected resolution. Sync happens only within blank periods thereby dividing the blank into three regions consisting of a front porch, sync time, and back porch. Borders only happen directly before the start of blank and directly after the end of blank. Borders are referred to as left, right, top, or bottom. The Pipe A timing generator has been adapted to offer interlace support for the generation of HSYNC and VSYNC relative timing to support downstream field identification. It has also been adapted to provide interlace timing support for 480i and PAL formats. The following sections detail the features supported by the Intel® 82854 GMCH.

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Intel D15343-003 manual Internal Graphic Display Interface, Pipe a Timing Generator Unit

Contents

Datasheet Intel 82854 Graphics Memory Controller Hub Gmch D15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Revision History Date Revision Description Intel 82854 Graphics Memory Controller Hub Gmch Overview Processor/Host Bus SupportMemory System System Interrupts Video Stream DecoderVideo Overlay Internal Graphics Features Display Intel 82854 Graphics Memory Controller Hub Gmch Graphic Power Management Power ManagementHub Interface to ICH4-M Intel 854 Chipset system block diagram Native Graphic mode Package Terminology Terms and DescriptionsTerm Description ICH4-M Reference Documents Reference DocumentsDocument Location Intel 82854 Graphics Memory Controller Hub Gmch System Architecture Intel 82854 Gmch DDR Sdram Memory Capacity Processor Host InterfaceGmch System Memory Interface Technology Width Gmch Analog Display Port Graphics FeaturesDisplay Features Gmch Integrated DVO Ports Hub Interface Address Decode Policies Ratio Gmch ClockingIntel 82854 Gmch Interface Clocks Bytes MB/s System Interrupts Notation Description Buffer Description Host Interface Signals Host Interface Signal Descriptions HITM# DRDY#HIT# HLOCK# RS20# RS20# Response type SRAS# DDR Sdram InterfaceDDR Sdram Interface Descriptions SCAS# Hub Interface Signals Hub Interface Signals Clocks DAC Clocking Display Power Management Signaling This signal is used onlyDpms Drefclk Internal Graphics Display Signals Digital Video Output B Dvob Port Signal DescriptionsDigital Video Output B Dvob Port Digital Video Output C Dvoc Port Signal Descriptions Digital Video Output C Dvoc Port Dvob and Dvoc Port Common Signal Descriptions Analog CRT Display Signal DescriptionsAnalog CRT Display General Purpose Input/Output Signals Gpio Signal Descriptions Voltage References, PLL Power Voltage References, PLL Power Hlvref HlrcompPswing Vcchl Conceptual Overview of the Platform Configuration Structure Device Number AssignmentGmch Function Bus #0, Device# Nomenclature for Access Attributes Nomenclature for Access Attributes Standard PCI Bus Configuration Mechanism Routing Configuration AccessesPCI Bus #0 Configuration Mechanism Register Definitions Primary PCI and Downstream Configuration MechanismDefault Value upon Reset Reserved Bits Configaddress Configuration Address Register I/O Mapped Registers Bit Descriptions Reserved Configdata Configuration Data Register Configuration Data Register Index Data Registers VGA I/O Mapped RegistersVGA I/O Mapped Register List Name Function Read @ Write @ Gmch Configuration Space Device #0, Function#0 Register Name Default Value AccessEnd Attbase VID Vendor Identification Register Did Device Identification RegisterBit Descriptions 150 Pcicmd PCI Command Register = Serr message is not generated by the Gmch for Device #0 PCI Status Register RID Register Identification Subc Sub Class Code Register BCC Base Class Code Register HDR Header Type RegisterSvid Subsystem Vendor Identification Register SID Subsystem Identification Register Capptr Capabilities Pointer Register Capid Capabilities Identification Register Device #0 Capability ID MDA Present MDAP-R/W Rrbar Access Enable-R/WGMC Gmch Miscellaneous Control Register Device #0 VGA Reserved Device #2 Function #1 Enable/Disable GGC Gmch Graphics Control Register Device #0Bit Dafc Device and Function Control Register Device #0 Fdhc Fixed Dram Hold Control Register Device #0Bit Description 17 PAM60 Programmable Attribute Map Register Device #0 Attribute Bit AssignmentBits 7 Bits 6 Bits 5 Bits 4 Description Reserved PAM Registers Video Buffer Area A0000h-BFFFFh PAM Registers and Associated System Memory SegmentsDOS Application Area 00000h-9FFFh Expansion Area C0000h-DFFFFh Extended System Bios Area E0000h-EFFFFh System Bios Area F0000h-FFFFFhSmram System Management RAM Control Register Device #0 Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Smicmd SMI Error Command Register Device #0 Bit Description Reserved SCI on Single-bit ECC Error Scicmd SCI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error SCI on Gmch Thermal Sensor Trip C2 state Gmch FSB Interface Power Management Control Reserved On Die Termination ODT Gating DisableReserved FSB Data Bus Power Management Control Shic Secondary Host Interface Control Register Device #0 HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DRT Dram Timing Register Device #0 DDR Internal Write to Read Command delay tWTRDDR Write Recovery time tWR Examples of usage Encoding CK between RD and RD commands Encoding CK between RD and WR commandsBack To Back Read-Read commands spacing DDR, different Rows Refresh Cycle Time tRFC Activate to Precharge delay tRAS, MAX Activate to Precharge delay tRAS, MINReserved CAS# Latency tCL Dynamic Memory Interface Power Management PCEn Page Close Enable TC Timer Control PDEn23CS# Signal Drive Control Rcven DLL shutdown disable Power State S1/S3 Refresh Control DRC Dram Controller Mode Register Device #0 Ddim DDR Sdram Data Integrity Mode 010 000001 011 For Double Data Rate DTC Dram Throttling Control Register Device #0 DDR Sdram Throttle Mode Tmode Wttc 2724 Thermal Power Throttle Control fields Enable High Priority Stream Throttling Enable Hpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpllcc Hpll Clock Control Register Device #0 Hpll VCO Change Sequence Initiate Bit DVO Port CRT Port Straps Read GFX CoreHPLLCC20 Rate Register Name Regs VID Vendor Identification Register Device #2 Did Device Identification Register Device #2 Pcicmd PCI Command Register Device #2 Pcists PCI Status Register Device #2 RID Revision Identification Register Device #2 CLS Cache Line Size Register Device #2 MLT Master Latency Timer Register Device #2CC Class Code Register Device #2 Base Class Code Basec 03=Display controller HDR Header Type Register Device #2 Bit Description Master Latency Timer Count Value ROPrefetchable Memory-RO Enable prefetching Gmadr Graphics Memory Range Address Register Device #2 Prefetchable Memory-RO Prevents prefetching Mmadr Memory Mapped Range Address Register Device #2Iobar I/O Base Address Register Device #2 Memory / IO Space-RO Romadr Video Bios ROM Base Address Registers Device #2 Svid Subsystem Vendor Identification Register Device #2SID Subsystem Identification Register Device #2 Intrline Interrupt Line Register Device #2 Intrpin Interrupt Pin Register Device #2Mingnt Minimum Grant Register Device #2 Pmcap Power Management Capabilities Register Device #2 Auxiliary Power Source Hardwired toMaxlat Maximum Latency Register Device #2 Pmcs Power Management Control/Status Register Device #2 Bits10 Power State System Memory Address Ranges Simplified View of System Address Map DOS Compatibility Area Detailed View of System Address Map Legacy VGA Ranges 0A0000h-0BFFFFh System Memory Segments and Their AttributesDOS Area 000000h-09FFFFh Compatible Smram Address Range 0A0000h-0BFFFFh Extended System Memory Area Extended System Bios Area 0E0000h-0EFFFFhSystem Bios Area 0F0000h-0FFFFFh Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh Pre-allocated System Memory 1 15 MB-16 MB WindowPre-allocated System Memory Attributes Comments Tseg Extended Smram Address Range Hseg and TsegHseg Dynamic Video Memory Technology Dvmt High Bios Area FFE00000h -FFFFFFFFh PCI Memory Address Range Top of Main System Memory to 4 GB System Management Mode SMM Memory Range SMM Space RestrictionsSMM Space Definition System Memory Shadowing 5 I/O Address SpaceSMM Space Transaction Handling Gmch Decode Rules and Cross-Bridge Address Mapping PCI I/O Address Mapping Hub Interface Accesses to Gmch that Cross Device Boundaries Hub Interface Decode Rules Cycles Initiated Using PCI Protocol Accesses to Gmch that Cross Device BoundariesInterface Decode Rules System Bus Interrupt Delivery Host Interface OverviewDynamic Bus Inversion Relation of DBI Bits to Data Bits System Memory Interface System Memory Organization and ConfigurationConfiguration Mechanism for DDR DIMMs Upstream Interrupt Messages Data Bytes on DDR Dimm Used for Programming Dram Registers DDR Sdram Performance DescriptionSystem Memory Register Programming Byte Function Integrated Graphics Overview 1 3D/2D Instruction Processing Viewport Transform and Perspective Divide Setup Engine2 3D Engine 2.3 3D Primitives and Data Formats Support Texture Engine Backface CullingScan Converter Perspective Correct Texture Support Texture Chromakey Anti-AliasingTexture Map Filtering Cubic Environment Mapping Raster EngineMultiple Texture Composition Bump Mapping Color Shading Modes Texture Map BlendingCombining Intrinsic and Specular Color Components Color Dithering Alpha Blending Color Buffer Formats Destination AlphaDepth Buffer Projective Textures 4 2D EngineStencil Buffer 4.1 256-Bit Pattern Fill and BLT Engine Planes and Engines Hardware Cursor Plane Native Graphic Mode onlyDual Display Usage Model Native Graphic Mode only Alpha Stretch BLT Overlay Plane Color Control Dynamic Bob and Weave Hardware Motion Compensation Video FunctionalityMPEG-2 Decoding Sub-picture Support Internal Graphic Display Interface Pipe a Timing Generator Unit 1.2 H, V timing signals for active and blank timing Arib Support Parameters HSYNC/VSYNC Field Timing Blend Function Interlaced Video Field displayInterlace support for Plane a graphics Arib 960 X 540 support Interlace support for Video Overlay Window DVO Control Data Bits Timing Register Switching Analog Display Port Characteristics Integrated RamdacDDC Display Data Channel 146 D15343-003 Power and Thermal Management General Description of Supported CPU States General Description of Acpi States Internal Thermal Sensor OverviewHysteresis Operation External Thermal Sensor Input Usage Strapping Configuration Strapping Signals and ConfigurationPin Name Strap Description Configuration Type Buffer Type Intel 82854 Gmch Straps for Frequency/CPU Configuration GST20FSB Freq DDR Freq Gfx Freq Core Vcc Ballout and Package Information VCC/VSS Voltage Groups Voltage Levels and Ball Out for Voltage GroupsName Voltage Level Ball out Row Column Signal Name Ballout Table 156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View