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Intel D15343-003 manual PAM Registers

Models: D15343-003

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

As an example, consider a BIOS that is implemented on the Expansion bus. During the initialization process, the BIOS can be shadowed in main system memory to increase the system performance. When BIOS is shadowed in main system memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to Write Only. The BIOS is shadowed by first doing a Read of that address. This Read is forwarded to the Expansion bus. The Host then does a Write of the same address, which is directed to main system memory. After the BIOS is shadowed, the attributes for that system memory area are set to Read Only so that all Writes are forwarded to the Expansion bus. Figure 4 and Table 21 show the PAM registers and the associated attribute bits.

Figure 4. PAM Registers

P A M 6

P A M 5

P A M 4

P A M 3

P A M 2

P A M 1

P A M 0

Offset 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h

7		6		5	4	3	2	1	0
	R	R	W E		R E	R	R	W E		RE

Reserved										Read Enable (R/W )
Reserved										1=Enable
W rite Enable (R/W)										0=Disable
W rite Enable (R/W)
1=Enable									Write Enable (R/W )
0=Disable									1=Enable
Read Enable (R/W )									0=Disable
Read Enable (R/W )

	1=Enable	Reserved
	1=Enable	Reserved
	0=Disable	Reserved
	0=Disable
		pam

62	D15343-003

Image 62

Intel D15343-003 manual PAM Registers

Contents

Datasheet Intel 82854 Graphics Memory Controller Hub GmchD15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Revision History Date Revision DescriptionIntel 82854 Graphics Memory Controller Hub Gmch Memory System OverviewProcessor/Host Bus Support Video Overlay System InterruptsVideo Stream Decoder Internal Graphics Features DisplayIntel 82854 Graphics Memory Controller Hub Gmch Hub Interface to ICH4-M Graphic Power ManagementPower Management Intel 854 Chipset system block diagram Native Graphic mode PackageTerm Description TerminologyTerms and Descriptions ICH4-M Document Location Reference DocumentsReference Documents Intel 82854 Graphics Memory Controller Hub Gmch System Architecture Intel 82854 GmchDDR Sdram Memory Capacity Processor Host InterfaceGmch System Memory Interface Technology WidthGmch Analog Display Port Graphics FeaturesDisplay Features Gmch Integrated DVO PortsHub Interface Address Decode PoliciesRatio Gmch ClockingIntel 82854 Gmch Interface Clocks Bytes MB/sSystem Interrupts Notation Description Buffer DescriptionHost Interface Signals Host Interface Signal DescriptionsHITM# DRDY#HIT# HLOCK#RS20# RS20# Response typeSRAS# DDR Sdram InterfaceDDR Sdram Interface Descriptions SCAS#Hub Interface Signals Hub Interface SignalsClocks DAC Clocking Display Power Management Signaling This signal is used onlyDpms DrefclkDigital Video Output B Dvob Port Internal Graphics Display SignalsDigital Video Output B Dvob Port Signal Descriptions Digital Video Output C Dvoc Port Signal Descriptions Digital Video Output C Dvoc PortAnalog CRT Display Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Signal Descriptions General Purpose Input/Output Signals Gpio Signal DescriptionsVoltage References, PLL Power Voltage References, PLL PowerHlvref HlrcompPswing VcchlGmch Function Bus #0, Device# Conceptual Overview of the Platform Configuration StructureDevice Number Assignment Nomenclature for Access Attributes Nomenclature for Access AttributesPCI Bus #0 Configuration Mechanism Standard PCI Bus Configuration MechanismRouting Configuration Accesses Register Definitions Primary PCI and Downstream Configuration MechanismDefault Value upon Reset Reserved BitsConfigaddress Configuration Address Register I/O Mapped RegistersBit Descriptions ReservedConfigdata Configuration Data Register Configuration Data RegisterIndex Data Registers VGA I/O Mapped RegistersVGA I/O Mapped Register List Name Function Read @ Write @End Gmch Configuration Space Device #0, Function#0Register Name Default Value Access Attbase Bit Descriptions 150 VID Vendor Identification RegisterDid Device Identification Register Pcicmd PCI Command Register = Serr message is not generated by the Gmch for Device #0PCI Status Register RID Register Identification Subc Sub Class Code RegisterSvid Subsystem Vendor Identification Register BCC Base Class Code RegisterHDR Header Type Register SID Subsystem Identification Register Capptr Capabilities Pointer RegisterCapid Capabilities Identification Register Device #0 Capability IDMDA Present MDAP-R/W Rrbar Access Enable-R/WGMC Gmch Miscellaneous Control Register Device #0 VGABit Reserved Device #2 Function #1 Enable/DisableGGC Gmch Graphics Control Register Device #0 Bit Description Dafc Device and Function Control Register Device #0Fdhc Fixed Dram Hold Control Register Device #0 Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved 17 PAM60 Programmable Attribute Map Register Device #0Attribute Bit Assignment PAM Registers Video Buffer Area A0000h-BFFFFh PAM Registers and Associated System Memory SegmentsDOS Application Area 00000h-9FFFh Expansion Area C0000h-DFFFFhSmram System Management RAM Control Register Device #0 Extended System Bios Area E0000h-EFFFFhSystem Bios Area F0000h-FFFFFh Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Smicmd SMI Error Command Register Device #0 Bit Description ReservedSCI on Single-bit ECC Error Scicmd SCI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error SCI on Gmch Thermal Sensor TripC2 state Gmch FSB Interface Power Management Control Reserved On Die Termination ODT Gating DisableReserved FSB Data Bus Power Management Control Shic Secondary Host Interface Control Register Device #0HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DRT Dram Timing Register Device #0 DDR Internal Write to Read Command delay tWTRDDR Write Recovery time tWR Examples of usageEncoding CK between RD and RD commands Encoding CK between RD and WR commandsBack To Back Read-Read commands spacing DDR, different Rows Refresh Cycle Time tRFCReserved CAS# Latency tCL Activate to Precharge delay tRAS, MAXActivate to Precharge delay tRAS, MIN Dynamic Memory Interface Power Management PCEn Page Close Enable TC Timer Control PDEn23CS# Signal Drive Control Rcven DLL shutdown disablePower State S1/S3 Refresh Control DRC Dram Controller Mode Register Device #0 Ddim DDR Sdram Data Integrity Mode010 000001 011For Double Data Rate DTC Dram Throttling Control Register Device #0 DDR Sdram Throttle Mode Tmode Wttc2724 Thermal Power Throttle Control fields Enable High Priority Stream Throttling EnableHpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpllcc Hpll Clock Control Register Device #0 Hpll VCO Change Sequence Initiate BitDVO Port CRT Port Straps Read GFX CoreHPLLCC20 RateRegister Name RegsVID Vendor Identification Register Device #2 Did Device Identification Register Device #2Pcicmd PCI Command Register Device #2 Pcists PCI Status Register Device #2 RID Revision Identification Register Device #2CLS Cache Line Size Register Device #2 MLT Master Latency Timer Register Device #2CC Class Code Register Device #2 Base Class Code Basec 03=Display controllerHDR Header Type Register Device #2 Bit Description Master Latency Timer Count Value ROPrefetchable Memory-RO Enable prefetching Gmadr Graphics Memory Range Address Register Device #2Prefetchable Memory-RO Prevents prefetching Mmadr Memory Mapped Range Address Register Device #2Iobar I/O Base Address Register Device #2 Memory / IO Space-ROSID Subsystem Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2Svid Subsystem Vendor Identification Register Device #2 Mingnt Minimum Grant Register Device #2 Intrline Interrupt Line Register Device #2Intrpin Interrupt Pin Register Device #2 Maxlat Maximum Latency Register Device #2 Pmcap Power Management Capabilities Register Device #2Auxiliary Power Source Hardwired to Pmcs Power Management Control/Status Register Device #2 Bits10 Power StateSystem Memory Address Ranges Simplified View of System Address MapDOS Compatibility Area Detailed View of System Address MapLegacy VGA Ranges 0A0000h-0BFFFFh System Memory Segments and Their AttributesDOS Area 000000h-09FFFFh Compatible Smram Address Range 0A0000h-0BFFFFhExtended System Memory Area Extended System Bios Area 0E0000h-0EFFFFhSystem Bios Area 0F0000h-0FFFFFh Monochrome Display Adapter MDA Range 0B0000h 0B7FFFhPre-allocated System Memory 1 15 MB-16 MB WindowPre-allocated System Memory Attributes CommentsTseg Extended Smram Address Range Hseg and TsegHseg Dynamic Video Memory Technology DvmtHigh Bios Area FFE00000h -FFFFFFFFh PCI Memory Address Range Top of Main System Memory to 4 GBSMM Space Definition System Management Mode SMM Memory RangeSMM Space Restrictions SMM Space Transaction Handling System Memory Shadowing5 I/O Address Space Gmch Decode Rules and Cross-Bridge Address Mapping PCI I/O Address MappingHub Interface Accesses to Gmch that Cross Device Boundaries Hub Interface Decode RulesInterface Decode Rules Cycles Initiated Using PCI ProtocolAccesses to Gmch that Cross Device Boundaries System Bus Interrupt Delivery Host Interface OverviewDynamic Bus Inversion Relation of DBI Bits to Data BitsSystem Memory Interface System Memory Organization and ConfigurationConfiguration Mechanism for DDR DIMMs Upstream Interrupt MessagesData Bytes on DDR Dimm Used for Programming Dram Registers DDR Sdram Performance DescriptionSystem Memory Register Programming Byte FunctionIntegrated Graphics Overview 1 3D/2D Instruction ProcessingViewport Transform and Perspective Divide Setup Engine2 3D Engine 2.3 3D Primitives and Data Formats SupportTexture Engine Backface CullingScan Converter Perspective Correct Texture SupportTexture Map Filtering Texture ChromakeyAnti-Aliasing Cubic Environment Mapping Raster EngineMultiple Texture Composition Bump MappingColor Shading Modes Texture Map BlendingCombining Intrinsic and Specular Color Components Color DitheringDepth Buffer Alpha BlendingColor Buffer Formats Destination Alpha Projective Textures 4 2D EngineStencil Buffer 4.1 256-Bit Pattern Fill and BLT EnginePlanes and Engines Hardware Cursor Plane Native Graphic Mode onlyDual Display Usage Model Native Graphic Mode only Alpha Stretch BLTOverlay Plane Color Control Dynamic Bob and WeaveHardware Motion Compensation Video FunctionalityMPEG-2 Decoding Sub-picture SupportInternal Graphic Display Interface Pipe a Timing Generator Unit1.2 H, V timing signals for active and blank timing Arib SupportParameters HSYNC/VSYNC Field TimingInterlace support for Plane a graphics Blend FunctionInterlaced Video Field display Arib 960 X 540 support Interlace support for Video Overlay Window DVO Control Data BitsTiming Register Switching DDC Display Data Channel Analog Display Port CharacteristicsIntegrated Ramdac 146 D15343-003 Power and Thermal Management General Description of Supported CPU States General Description of Acpi StatesHysteresis Operation Internal Thermal SensorOverview External Thermal Sensor Input UsagePin Name Strap Description Configuration Type Buffer Type Strapping ConfigurationStrapping Signals and Configuration FSB Freq DDR Freq Gfx Freq Core Vcc Intel 82854 Gmch Straps for Frequency/CPU ConfigurationGST20 Ballout and Package Information Name Voltage Level Ball out VCC/VSS Voltage GroupsVoltage Levels and Ball Out for Voltage Groups Row Column Signal Name Ballout Table156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Package Mechanical InformationIntel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View