Intel D15343-003 manual Drdy#, Hit#, Hitm#, Hlock#, Htrdy#

				Signal Description
DRDY#	I/O	Data Ready: Asserted for each cycle that data is transferred.
	AGTL+
HA[31:3]#	I/O	Host Address Bus: HA[31:3]# connects to the CPU address bus. During
	AGTL+	processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]#
		during snoop cycles on behalf of Hub interface. HA[31:3]# are
		transferred at 2x rate. Note that the address is inverted on the CPU bus.
HADSTB[1:0]#	I/O	Host Address Strobe: HA[31:3]# connects to the CPU address bus.
	AGTL+	During CPU cycles, the source synchronous strobes are used to transfer
		HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
		Strobe	Address Bits
		HADSTB[0]#	HA[16:3]#, HREQ[4:0]#
		HADSTB[1]#	HA[31:17]#
HD[63:0]#	I/O	Host Data: These signals are connected to the CPU data bus.
	AGTL+	HD[63:0]# are transferred at 4x rate. Note that the data signals are
		inverted on the CPU bus.
HDSTBP[3:0]#	I/O	Differential Host Data Strobes: The differential source synchronous
HDSTBN[3:0]#	AGTL+	strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x
		transfer rate.
		Strobe		Data Bits
		HDSTBP[3]#, HDSTBN[3]#		HD[63:48]#, DINV[3]#
		HDSTBP[2]#, HDSTBN[2]#		HD[47:32]#, DINV[2]#
		HDSTBP[1]#, HDSTBN[1]#		HD[31:16]#, DINV[1]#
		HDSTBP[0]#, HDSTBN[0]#		HD[15:0]#, DINV[0]#
HIT#	I/O	Hit: Indicates that a caching agent holds an unmodified version of the
	AGTL+	requested line. Also, driven in conjunction with HITM# by the target to
		extend the snoop window.
HITM#	I/O	Hit Modified: Indicates that a caching agent holds a modified version of
	AGTL+	the requested line and that this agent assumes responsibility for
		providing the line. Also, driven in conjunction with HIT# to extend the
		snoop window.
HLOCK#	I/O	Host Lock: All CPU bus cycles sampled with the assertion of HLOCK#
	AGTL+	and ADS#, until the negation of HLOCK# must be atomic; that is, no Hub
		interface snoopable access to system memory is allowed when HLOCK#
		is asserted by the CPU.
HREQ[4:0]#	I/O	Host Request Command: Defines the attributes of the request.
	AGTL+	HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent
		during both halves of the Request Phase. In the first half the signals
		define the transaction type to a level of detail that is sufficient to begin a
		snoop request. In the second half the signals carry additional information
		to define the complete transaction type.
		The transactions supported by the GMCH Host Bridge are defined in the
		Host Interface section of this document.
HTRDY#	O	Host Target Ready: Indicates that the target of the processor
	AGTL+	transaction is able to enter the data transfer phase.

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