Intel D15343-003 manual Strapping Configuration, Strapping Signals and Configuration

Intel® 82854 GMCH Strap Pins

8.0Intel® 82854 GMCH Strap Pins

8.1Strapping Configuration

Table 33.	Strapping Signals and Configuration
Pin Name	Strap Description	Configuration	I/F Type	Buffer Type
ADDID[0]	Native Graphic Mode	ADDID[0] = 0, Reserved	DVO	IN
	select	ADDID[0] = 1, the Intel® 82854
		GMCH is strapped to operate
		under Native Graphic Mode
HSYNC	XOR Chain Test	Low = Normal Ops (Default)	GPIO	OUT
		High = XOR Test On
VSYNC	ALL Z Test	Low = Normal Ops (Default)	GPIO	OUT
		High = AllZ Test On
LCLKCTLB	VTT Voltage Select	Low = Default	GPIO	OUT
		High = Reserved
DVODETECT	*DVO Select (If	Low = DVO (Default)	DVO	BI
	DVODETECT=0 during	High = Reserved
	Reset, ADDID[7:0] is
	latched to the ADDID
	Register)
GST[2]	* Clock Config: Bit_2	Please refer to Device #0	DVO	Out:
		Function #3 (HPLLCC Register)		0) Before CPURST#, there is an
		for proper GST[2:0] settings
				internal pull-down
		Please refer to Table 34 for
				1) Just out of CPURST#: These
		detail configurations on Intel
				pins are Hi-Z
		854 Straps for Frequency/CPU
				2) C3: these pins are Hi-Z
				3) S1-M: these pins are Hi-Z
				4) Internal GFX D1/D3: these pins
				are Hi-Z
				5) S3: these pins are Power down
				6) S4/S5: these pins are Power
				down
GST[1]	* Clock Config: Bit_1
GST[0]	* Clock Config: Bit_0
*	Please refer to Device #0 Function #2 (ADD_ID – ADD Identification Register) for proper Native Graphic
	Mode settings.
	External pull-ups/downs will be required on the board to enable the non-default state of the straps.

Note: All strap signals are sampled with respect to the leading edge of the Intel® 82854 GMCH PWROK In signal.

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