Intel D15343-003 manual Clocks

Signal Description

3.4Clocks

Table 8. Clock Signals

Signal Name	Type	Description
Host Processor Clocking
BCLK	I	Differential Host Clock In: These pins receive a buffered host clock
BCLK#	CMOS	from the external clock synthesizer. This clock is used by all of the
		GMCH logic that are in the Host clock domain (Host, Hub and system
		memory). The clock is also the reference clock for the graphics core
		PLL. This is a low voltage differential input.
System Memory Clocking
SCK[5:0]	O	Differential DDR SDRAM Clock: SCK and SCK# pairs are differential
	SSTL_2	clock outputs. The crossing of the positive edge of SCK and the
		negative edge of SCK# is used to sample the address and control
		signals on the DDR SDRAM. There are 3 pairs to each DDR DIMM.
SCK[5:0]#	O	Complementary Differential DDR SDRAM Clock: These are the
	SSTL_2	complimentary differential DDR SDRAM clock signals.
DVO/Hub Input Clocking
GCLKIN	I	Input Clock: 66-MHz, 3.3-V input clock from external buffer DVO/Hub
	CMOS	interface.
DVO Clocking
DVOBCLK	O	Differential DVO Clock Output: These pins provide a differential pair
DVOBCLK#	DVO	reference clock that can run up to 165-MHz.
		DVOBCLK corresponds to the primary clock out.
		DVOBCLK# corresponds to the primary complementary clock out.
		DVOBCLK and DVOBCLK# should be left as NC (“Not Connected”) if
		the DVO B port is not implemented.
DVOCCLK	O	Differential DVO Clock Output: These pins provide a differential pair
DVOCCLK#	DVO	reference clock that can run up to 165-MHz.
		DVOCCLK corresponds to the primary clock out.
		DVOCCLK# corresponds to the primary complementary clock out.
		DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if
		the DVO C port is not implemented.
DVOBCCLKINT	I	DVOBC Pixel Clock Input/Interrupt: This signal may be selected as
	DVO	the reference input to either dot clock PLL (DPLL) or may be
		configured as an interrupt input. A TV-out device can provide the clock
		reference. The maximum input frequency for this signal is 148.5 -MHz.
		DVOBC Pixel Clock Input: When selected as the dot clock PLL (DPLL)
		reference input, this clock reference input supports SSC clocking for
		DVO LVDS devices.
		DVOBC Interrupt: When configured as an interrupt input, this interrupt
		can support either DVOB or DVOC.
		DVOBCCLKINT needs to be pulled down if the signal is NOT used.

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