Intel D15343-003 manual Interface Decode Rules, Cycles Initiated Using PCI Protocol

Intel® 82854 Graphics Memory Controller Hub (GMCH)

5.4.7.2Interface Decode Rules

Cycles Initiated Using PCI Protocol

The GMCH does not support any PCI access targeting Hub interface. The GMCH will claim PCI initiated memory read and write transactions decoded to the main DDR SDRAM range. All other memory read and write requests will be master-aborted by the PCI initiator as a consequence of GMCH not responding to a transaction.

Under certain conditions, the GMCH restricts access to the DOS Compatibility ranges governed by the PAM registers by distinguishing access type and destination bus. The GMCH accepts PCI write transactions to the compatibility ranges if the PAM designates DDR SDRAM as writeable. If accesses to a range are not write enabled by the PAM, the GMCH does not respond and the cycle will result in a master-abort. The GMCH accepts PCI read transactions to the compatibility ranges if the PAM designates DDR SDRAM as readable. If accesses to a range are not read enabled by the PAM, the GMCH does not respond and the cycle will result in a master-abort.

If agent on PCI issues an I/O or PCI Special Cycle transaction, the GMCH will not respond and cycle will result in a master-abort. The GMCH will accept PCI configuration cycles to the internal GMCH devices as part of the PCI configuration/co-pilot mode mechanism.

Accesses to GMCH that Cross Device Boundaries

For FRAME# accesses, when a PCI master gets disconnected it will resume at the new address which allows the cycle to be routed to or claimed by the new target. Therefore accesses should be disconnected by the target on potential device boundaries. The GMCH will disconnect PCI transactions on 4-kB boundaries.

SBA accesses are limited to 256 bytes and must hit DDR SDRAM. Accesses are dispatched to DDR SDRAM on naturally aligned 32 byte block boundaries. The portion of the request that hits a valid address will complete normally. The portion of a read access that hits an invalid address will be remapped to address 0h, return data from address 0h, and set the IAAF error flag. The portion of a write access that hits an invalid address will be remapped to memory address 0h with BE's deasserted (effectively dropped "on the floor") and set the IAAF error flag.

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