PCI Status Register Overview for Intel Switch Models D15343-003

Register Description

4.8.4PCI Status Register

Address Offset:	06-07h
Default Value:	0090h
Access:	Read only, Read/WriteClear
Size:	16 bits

PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.

Bit	Descriptions

15	Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0.
	Writes to this bit position have no effect.

14	Signaled System Error (SSE): R/WC. This bit is set to 1 when GMCH Device #0 generates an
	SERR message over HI for any enabled Device #0 error condition. Device #0 error conditions are
	enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset from the
	PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit.

13	Received Master Abort Status (RMAS): R/WC. This bit is set when the GMCH generates a HI
	request that receives a Master Abort completion packet or Master Abort Special Cycle. Software
	clears this bit by writing a 1 to it.

12	Received Target Abort Status (RTAS): R/WC. This bit is set when the GMCH generates a HI
	request that receives a Target Abort completion packet or Target Abort Special Cycle. Software
	clears this bit by writing a 1 to it. If bit 6 in the ERRCMD is set to a one and an Serr# special cycle
	is generated on the HI bus.

11	Signaled Target Abort Status (STAS): The GMCH will not generate a Target Abort HI
	completion packet or Special Cycle. This bit is not implemented in the GMCH and is hardwired to
	a 0. Writes to this bit position have no effect.

10:9	DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes to these bit positions have no
	affect. Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode)
	so that the GMCH does not limit optimum DEVSEL timing for PCI_A.

8	Master Data Parity Error Detected (DPD): PERR signaling and messaging are not implemented
	by the GMCH therefore this bit is hardwired to 0. Writes to this bit position have no effect.

7	Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no
	effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-
	back capability) so that the GMCH does not limit the optimum setting for PCI_A.

6:5	Reserved

4	Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that
	this device/function implements a list of new capabilities. A list of new capabilities is accessed via
	register CAPPTR at configuration address offset 34h.

3:0	Reserved

D15343-003

53

Image 53

Intel D15343-003 manual PCI Status Register

Contents

Intel 82854 Graphics Memory Controller Hub Gmch Datasheet D15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Date Revision Description Revision History Intel 82854 Graphics Memory Controller Hub Gmch Memory System OverviewProcessor/Host Bus Support Video Overlay System InterruptsVideo Stream Decoder Display Internal Graphics Features Intel 82854 Graphics Memory Controller Hub Gmch Hub Interface to ICH4-M Graphic Power ManagementPower Management Package Intel 854 Chipset system block diagram Native Graphic mode Term Description TerminologyTerms and Descriptions ICH4-M Document Location Reference DocumentsReference Documents Intel 82854 Graphics Memory Controller Hub Gmch Intel 82854 Gmch System Architecture Gmch System Memory Interface Processor Host InterfaceDDR Sdram Memory Capacity Technology Width Display Features Graphics FeaturesGmch Analog Display Port Gmch Integrated DVO Ports Address Decode Policies Hub Interface Intel 82854 Gmch Interface Clocks Gmch ClockingRatio Bytes MB/s System Interrupts Buffer Description Notation Description Host Interface Signal Descriptions Host Interface Signals HIT# DRDY#HITM# HLOCK# RS20# Response type RS20# DDR Sdram Interface Descriptions DDR Sdram InterfaceSRAS# SCAS# Hub Interface Signals Hub Interface Signals Clocks Dpms Display Power Management Signaling This signal is used onlyDAC Clocking Drefclk Digital Video Output B Dvob Port Internal Graphics Display SignalsDigital Video Output B Dvob Port Signal Descriptions Digital Video Output C Dvoc Port Digital Video Output C Dvoc Port Signal Descriptions Analog CRT Display Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Signal Descriptions Gpio Signal Descriptions General Purpose Input/Output Signals Voltage References, PLL Power Voltage References, PLL Power Pswing HlrcompHlvref Vcchl Gmch Function Bus #0, Device# Conceptual Overview of the Platform Configuration StructureDevice Number Assignment Nomenclature for Access Attributes Nomenclature for Access Attributes PCI Bus #0 Configuration Mechanism Standard PCI Bus Configuration MechanismRouting Configuration Accesses Default Value upon Reset Primary PCI and Downstream Configuration MechanismRegister Definitions Reserved Bits I/O Mapped Registers Configaddress Configuration Address Register Reserved Bit Descriptions Configuration Data Register Configdata Configuration Data Register VGA I/O Mapped Register List VGA I/O Mapped RegistersIndex Data Registers Name Function Read @ Write @ End Gmch Configuration Space Device #0, Function#0Register Name Default Value Access Attbase Bit Descriptions 150 VID Vendor Identification RegisterDid Device Identification Register = Serr message is not generated by the Gmch for Device #0 Pcicmd PCI Command Register PCI Status Register Subc Sub Class Code Register RID Register Identification Svid Subsystem Vendor Identification Register BCC Base Class Code RegisterHDR Header Type Register Capptr Capabilities Pointer Register SID Subsystem Identification Register Capability ID Capid Capabilities Identification Register Device #0 GMC Gmch Miscellaneous Control Register Device #0 Rrbar Access Enable-R/WMDA Present MDAP-R/W VGA Bit Reserved Device #2 Function #1 Enable/DisableGGC Gmch Graphics Control Register Device #0 Bit Description Dafc Device and Function Control Register Device #0Fdhc Fixed Dram Hold Control Register Device #0 Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved 17 PAM60 Programmable Attribute Map Register Device #0Attribute Bit Assignment PAM Registers DOS Application Area 00000h-9FFFh PAM Registers and Associated System Memory SegmentsVideo Buffer Area A0000h-BFFFFh Expansion Area C0000h-DFFFFh Smram System Management RAM Control Register Device #0 Extended System Bios Area E0000h-EFFFFhSystem Bios Area F0000h-FFFFFh Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Bit Description Reserved Smicmd SMI Error Command Register Device #0 Reserved SCI on Multiple-bit ECC Error Scicmd SCI Error Command Register Device #0SCI on Single-bit ECC Error SCI on Gmch Thermal Sensor Trip Reserved FSB Data Bus Power Management Control Reserved On Die Termination ODT Gating DisableC2 state Gmch FSB Interface Power Management Control Shic Secondary Host Interface Control Register Device #0 HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DDR Write Recovery time tWR DDR Internal Write to Read Command delay tWTRDRT Dram Timing Register Device #0 Examples of usage Back To Back Read-Read commands spacing DDR, different Rows Encoding CK between RD and WR commandsEncoding CK between RD and RD commands Refresh Cycle Time tRFC Reserved CAS# Latency tCL Activate to Precharge delay tRAS, MAXActivate to Precharge delay tRAS, MIN CS# Signal Drive Control PCEn Page Close Enable TC Timer Control PDEn23Dynamic Memory Interface Power Management Rcven DLL shutdown disable Power State S1/S3 Refresh Control Ddim DDR Sdram Data Integrity Mode DRC Dram Controller Mode Register Device #0 001 000010 011 For Double Data Rate DTC Dram Throttling Control Register Device #0 Wttc DDR Sdram Throttle Mode Tmode 2724 High Priority Stream Throttling Enable Thermal Power Throttle Control fields Enable Hpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpll VCO Change Sequence Initiate Bit Hpllcc Hpll Clock Control Register Device #0 HPLLCC20 Straps Read GFX CoreDVO Port CRT Port Rate Regs Register Name Did Device Identification Register Device #2 VID Vendor Identification Register Device #2 Pcicmd PCI Command Register Device #2 RID Revision Identification Register Device #2 Pcists PCI Status Register Device #2 CC Class Code Register Device #2 MLT Master Latency Timer Register Device #2CLS Cache Line Size Register Device #2 Base Class Code Basec 03=Display controller Prefetchable Memory-RO Enable prefetching Bit Description Master Latency Timer Count Value ROHDR Header Type Register Device #2 Gmadr Graphics Memory Range Address Register Device #2 Iobar I/O Base Address Register Device #2 Mmadr Memory Mapped Range Address Register Device #2Prefetchable Memory-RO Prevents prefetching Memory / IO Space-RO SID Subsystem Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2Svid Subsystem Vendor Identification Register Device #2 Mingnt Minimum Grant Register Device #2 Intrline Interrupt Line Register Device #2Intrpin Interrupt Pin Register Device #2 Maxlat Maximum Latency Register Device #2 Pmcap Power Management Capabilities Register Device #2Auxiliary Power Source Hardwired to Bits10 Power State Pmcs Power Management Control/Status Register Device #2 Simplified View of System Address Map System Memory Address Ranges Detailed View of System Address Map DOS Compatibility Area DOS Area 000000h-09FFFFh System Memory Segments and Their AttributesLegacy VGA Ranges 0A0000h-0BFFFFh Compatible Smram Address Range 0A0000h-0BFFFFh System Bios Area 0F0000h-0FFFFFh Extended System Bios Area 0E0000h-0EFFFFhExtended System Memory Area Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh Pre-allocated System Memory 1 15 MB-16 MB WindowPre-allocated System Memory Attributes Comments Hseg Extended Smram Address Range Hseg and TsegTseg Dynamic Video Memory Technology Dvmt PCI Memory Address Range Top of Main System Memory to 4 GB High Bios Area FFE00000h -FFFFFFFFh SMM Space Definition System Management Mode SMM Memory RangeSMM Space Restrictions SMM Space Transaction Handling System Memory Shadowing5 I/O Address Space PCI I/O Address Mapping Gmch Decode Rules and Cross-Bridge Address Mapping Hub Interface Decode Rules Hub Interface Accesses to Gmch that Cross Device Boundaries Interface Decode Rules Cycles Initiated Using PCI ProtocolAccesses to Gmch that Cross Device Boundaries Dynamic Bus Inversion Host Interface OverviewSystem Bus Interrupt Delivery Relation of DBI Bits to Data Bits Configuration Mechanism for DDR DIMMs System Memory Organization and ConfigurationSystem Memory Interface Upstream Interrupt Messages System Memory Register Programming DDR Sdram Performance DescriptionData Bytes on DDR Dimm Used for Programming Dram Registers Byte Function 1 3D/2D Instruction Processing Integrated Graphics Overview 2 3D Engine Setup EngineViewport Transform and Perspective Divide 2.3 3D Primitives and Data Formats Support Scan Converter Backface CullingTexture Engine Perspective Correct Texture Support Texture Map Filtering Texture ChromakeyAnti-Aliasing Multiple Texture Composition Raster EngineCubic Environment Mapping Bump Mapping Combining Intrinsic and Specular Color Components Texture Map BlendingColor Shading Modes Color Dithering Depth Buffer Alpha BlendingColor Buffer Formats Destination Alpha Stencil Buffer 4 2D EngineProjective Textures 4.1 256-Bit Pattern Fill and BLT Engine Dual Display Usage Model Native Graphic Mode only Hardware Cursor Plane Native Graphic Mode onlyPlanes and Engines Alpha Stretch BLT Overlay Plane Dynamic Bob and Weave Color Control MPEG-2 Decoding Video FunctionalityHardware Motion Compensation Sub-picture Support Pipe a Timing Generator Unit Internal Graphic Display Interface Arib Support 1.2 H, V timing signals for active and blank timing HSYNC/VSYNC Field Timing Parameters Interlace support for Plane a graphics Blend FunctionInterlaced Video Field display Arib 960 X 540 support DVO Control Data Bits Interlace support for Video Overlay Window Timing Register Switching DDC Display Data Channel Analog Display Port CharacteristicsIntegrated Ramdac 146 D15343-003 Power and Thermal Management General Description of Acpi States General Description of Supported CPU States Hysteresis Operation Internal Thermal SensorOverview Usage External Thermal Sensor Input Pin Name Strap Description Configuration Type Buffer Type Strapping ConfigurationStrapping Signals and Configuration FSB Freq DDR Freq Gfx Freq Core Vcc Intel 82854 Gmch Straps for Frequency/CPU ConfigurationGST20 Ballout and Package Information Name Voltage Level Ball out VCC/VSS Voltage GroupsVoltage Levels and Ball Out for Voltage Groups Ballout Table Row Column Signal Name 156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View