Maxlat Maximum Latency Register Device #2 | Intel D15343-003

Register Description

4.11.19MAXLAT – Maximum Latency Register (Device #2)

Address Offset:		3Fh
Default Value:		00h
Access:		Read Only
Size:		8 bits

Bit	Description

7:0	Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it
	needs to access the PCI bus.

4.11.20PMCAP – Power Management Capabilities Register (Device #2)

Address Offset:		D2-D3h
Default Value:		0221h
Access:		Read Only
Size:		16 bits

Bit	Description

15:11	PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired
	to 0 to indicate that the IGD does not assert the PME# signal.

10:6	Reserved

5	Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD
	is required before generic class device driver is to use it.

4	Auxiliary Power Source: Hardwired to 0.

3	PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation.

2:0	Version: Hardwired to 001b to indicate there are 4 bytes of power management registers
	implemented.

D15343-003

109

Image 109

Intel D15343-003 manual Maxlat Maximum Latency Register Device #2, Pmcap Power Management Capabilities Register Device #2

Contents

Intel 82854 Graphics Memory Controller Hub Gmch Datasheet D15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Date Revision Description Revision History Intel 82854 Graphics Memory Controller Hub Gmch Processor/Host Bus Support OverviewMemory System Video Stream Decoder System InterruptsVideo Overlay Display Internal Graphics Features Intel 82854 Graphics Memory Controller Hub Gmch Power Management Graphic Power ManagementHub Interface to ICH4-M Package Intel 854 Chipset system block diagram Native Graphic mode Terms and Descriptions TerminologyTerm Description ICH4-M Reference Documents Reference DocumentsDocument Location Intel 82854 Graphics Memory Controller Hub Gmch Intel 82854 Gmch System Architecture Gmch System Memory Interface Processor Host InterfaceDDR Sdram Memory Capacity Technology Width Display Features Graphics FeaturesGmch Analog Display Port Gmch Integrated DVO Ports Address Decode Policies Hub Interface Intel 82854 Gmch Interface Clocks Gmch ClockingRatio Bytes MB/s System Interrupts Buffer Description Notation Description Host Interface Signal Descriptions Host Interface Signals HIT# DRDY#HITM# HLOCK# RS20# Response type RS20# DDR Sdram Interface Descriptions DDR Sdram InterfaceSRAS# SCAS# Hub Interface Signals Hub Interface Signals Clocks Dpms Display Power Management Signaling This signal is used onlyDAC Clocking Drefclk Digital Video Output B Dvob Port Signal Descriptions Internal Graphics Display SignalsDigital Video Output B Dvob Port Digital Video Output C Dvoc Port Digital Video Output C Dvoc Port Signal Descriptions Analog CRT Display Signal Descriptions Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Gpio Signal Descriptions General Purpose Input/Output Signals Voltage References, PLL Power Voltage References, PLL Power Pswing HlrcompHlvref Vcchl Device Number Assignment Conceptual Overview of the Platform Configuration StructureGmch Function Bus #0, Device# Nomenclature for Access Attributes Nomenclature for Access Attributes Routing Configuration Accesses Standard PCI Bus Configuration MechanismPCI Bus #0 Configuration Mechanism Default Value upon Reset Primary PCI and Downstream Configuration MechanismRegister Definitions Reserved Bits I/O Mapped Registers Configaddress Configuration Address Register Reserved Bit Descriptions Configuration Data Register Configdata Configuration Data Register VGA I/O Mapped Register List VGA I/O Mapped RegistersIndex Data Registers Name Function Read @ Write @ Register Name Default Value Access Gmch Configuration Space Device #0, Function#0End Attbase Did Device Identification Register VID Vendor Identification RegisterBit Descriptions 150 = Serr message is not generated by the Gmch for Device #0 Pcicmd PCI Command Register PCI Status Register Subc Sub Class Code Register RID Register Identification HDR Header Type Register BCC Base Class Code RegisterSvid Subsystem Vendor Identification Register Capptr Capabilities Pointer Register SID Subsystem Identification Register Capability ID Capid Capabilities Identification Register Device #0 GMC Gmch Miscellaneous Control Register Device #0 Rrbar Access Enable-R/WMDA Present MDAP-R/W VGA GGC Gmch Graphics Control Register Device #0 Reserved Device #2 Function #1 Enable/DisableBit Fdhc Fixed Dram Hold Control Register Device #0 Dafc Device and Function Control Register Device #0Bit Description Attribute Bit Assignment 17 PAM60 Programmable Attribute Map Register Device #0Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved PAM Registers DOS Application Area 00000h-9FFFh PAM Registers and Associated System Memory SegmentsVideo Buffer Area A0000h-BFFFFh Expansion Area C0000h-DFFFFh System Bios Area F0000h-FFFFFh Extended System Bios Area E0000h-EFFFFhSmram System Management RAM Control Register Device #0 Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Bit Description Reserved Smicmd SMI Error Command Register Device #0 Reserved SCI on Multiple-bit ECC Error Scicmd SCI Error Command Register Device #0SCI on Single-bit ECC Error SCI on Gmch Thermal Sensor Trip Reserved FSB Data Bus Power Management Control Reserved On Die Termination ODT Gating DisableC2 state Gmch FSB Interface Power Management Control Shic Secondary Host Interface Control Register Device #0 HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DDR Write Recovery time tWR DDR Internal Write to Read Command delay tWTRDRT Dram Timing Register Device #0 Examples of usage Back To Back Read-Read commands spacing DDR, different Rows Encoding CK between RD and WR commandsEncoding CK between RD and RD commands Refresh Cycle Time tRFC Activate to Precharge delay tRAS, MIN Activate to Precharge delay tRAS, MAXReserved CAS# Latency tCL CS# Signal Drive Control PCEn Page Close Enable TC Timer Control PDEn23Dynamic Memory Interface Power Management Rcven DLL shutdown disable Power State S1/S3 Refresh Control Ddim DDR Sdram Data Integrity Mode DRC Dram Controller Mode Register Device #0 001 000010 011 For Double Data Rate DTC Dram Throttling Control Register Device #0 Wttc DDR Sdram Throttle Mode Tmode 2724 High Priority Stream Throttling Enable Thermal Power Throttle Control fields Enable Hpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpll VCO Change Sequence Initiate Bit Hpllcc Hpll Clock Control Register Device #0 HPLLCC20 Straps Read GFX CoreDVO Port CRT Port Rate Regs Register Name Did Device Identification Register Device #2 VID Vendor Identification Register Device #2 Pcicmd PCI Command Register Device #2 RID Revision Identification Register Device #2 Pcists PCI Status Register Device #2 CC Class Code Register Device #2 MLT Master Latency Timer Register Device #2CLS Cache Line Size Register Device #2 Base Class Code Basec 03=Display controller Prefetchable Memory-RO Enable prefetching Bit Description Master Latency Timer Count Value ROHDR Header Type Register Device #2 Gmadr Graphics Memory Range Address Register Device #2 Iobar I/O Base Address Register Device #2 Mmadr Memory Mapped Range Address Register Device #2Prefetchable Memory-RO Prevents prefetching Memory / IO Space-RO Svid Subsystem Vendor Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2SID Subsystem Identification Register Device #2 Intrpin Interrupt Pin Register Device #2 Intrline Interrupt Line Register Device #2Mingnt Minimum Grant Register Device #2 Auxiliary Power Source Hardwired to Pmcap Power Management Capabilities Register Device #2Maxlat Maximum Latency Register Device #2 Bits10 Power State Pmcs Power Management Control/Status Register Device #2 Simplified View of System Address Map System Memory Address Ranges Detailed View of System Address Map DOS Compatibility Area DOS Area 000000h-09FFFFh System Memory Segments and Their AttributesLegacy VGA Ranges 0A0000h-0BFFFFh Compatible Smram Address Range 0A0000h-0BFFFFh System Bios Area 0F0000h-0FFFFFh Extended System Bios Area 0E0000h-0EFFFFhExtended System Memory Area Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh Pre-allocated System Memory 1 15 MB-16 MB WindowPre-allocated System Memory Attributes Comments Hseg Extended Smram Address Range Hseg and TsegTseg Dynamic Video Memory Technology Dvmt PCI Memory Address Range Top of Main System Memory to 4 GB High Bios Area FFE00000h -FFFFFFFFh SMM Space Restrictions System Management Mode SMM Memory RangeSMM Space Definition 5 I/O Address Space System Memory ShadowingSMM Space Transaction Handling PCI I/O Address Mapping Gmch Decode Rules and Cross-Bridge Address Mapping Hub Interface Decode Rules Hub Interface Accesses to Gmch that Cross Device Boundaries Accesses to Gmch that Cross Device Boundaries Cycles Initiated Using PCI ProtocolInterface Decode Rules Dynamic Bus Inversion Host Interface OverviewSystem Bus Interrupt Delivery Relation of DBI Bits to Data Bits Configuration Mechanism for DDR DIMMs System Memory Organization and ConfigurationSystem Memory Interface Upstream Interrupt Messages System Memory Register Programming DDR Sdram Performance DescriptionData Bytes on DDR Dimm Used for Programming Dram Registers Byte Function 1 3D/2D Instruction Processing Integrated Graphics Overview 2 3D Engine Setup EngineViewport Transform and Perspective Divide 2.3 3D Primitives and Data Formats Support Scan Converter Backface CullingTexture Engine Perspective Correct Texture Support Anti-Aliasing Texture ChromakeyTexture Map Filtering Multiple Texture Composition Raster EngineCubic Environment Mapping Bump Mapping Combining Intrinsic and Specular Color Components Texture Map BlendingColor Shading Modes Color Dithering Color Buffer Formats Destination Alpha Alpha BlendingDepth Buffer Stencil Buffer 4 2D EngineProjective Textures 4.1 256-Bit Pattern Fill and BLT Engine Dual Display Usage Model Native Graphic Mode only Hardware Cursor Plane Native Graphic Mode onlyPlanes and Engines Alpha Stretch BLT Overlay Plane Dynamic Bob and Weave Color Control MPEG-2 Decoding Video FunctionalityHardware Motion Compensation Sub-picture Support Pipe a Timing Generator Unit Internal Graphic Display Interface Arib Support 1.2 H, V timing signals for active and blank timing HSYNC/VSYNC Field Timing Parameters Interlaced Video Field display Blend FunctionInterlace support for Plane a graphics Arib 960 X 540 support DVO Control Data Bits Interlace support for Video Overlay Window Timing Register Switching Integrated Ramdac Analog Display Port CharacteristicsDDC Display Data Channel 146 D15343-003 Power and Thermal Management General Description of Acpi States General Description of Supported CPU States Overview Internal Thermal SensorHysteresis Operation Usage External Thermal Sensor Input Strapping Signals and Configuration Strapping ConfigurationPin Name Strap Description Configuration Type Buffer Type GST20 Intel 82854 Gmch Straps for Frequency/CPU ConfigurationFSB Freq DDR Freq Gfx Freq Core Vcc Ballout and Package Information Voltage Levels and Ball Out for Voltage Groups VCC/VSS Voltage GroupsName Voltage Level Ball out Ballout Table Row Column Signal Name 156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View