Intel D15343-003 manual Nomenclature for Access Attributes

Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.2Nomenclature for Access Attributes

Table 16 provides the nomenclature for the access attributes.

Table 16. Nomenclature for Access Attributes

RO	Read Only. If a register is Read Only, Writes to this register have no effect.
R/W	Read/Write. A register with this attribute can be Read and Written.
R/W/L	Read/Write/Lock. A register with this attribute can be Read, Written, and Locked.
R/WC	Read/Write Clear. A register bit with this attribute can be Read and Written.
	However, a Write of a 1 clears (sets to 0) the corresponding bit and a Write of a 0
	has no effect.
R/WO	Read/Write Once. A register bit with this attribute can be Written to only once
	after power up. After the first Write, this bit becomes Read Only.
L	Lock. A register bit with this attribute becomes Read Only after a Lock bit is set.
Reserved Bits	Some of the GMCH registers described in this section contain Reserved bits.
	These bits are labeled "Reserved”. Software must deal correctly with fields that are
	Reserved. On Reads, software must use appropriate masks to extract the defined
	bits and not rely on Reserved bits being of any particular value. On Writes,
	software must ensure that the values of Reserved bit positions are preserved. That
	is, the values of Reserved bit positions must first be Read, Merged with the new
	values for other bit positions and then Written back. Note the software does not
	need to perform Read, Merge, and Write operations for the Configuration Address
	register.
Reserved Registers	In addition to Reserved bits within a register, the GMCH contains address locations
	in the configuration space of the Host-Hub Interface Bridge entity that are marked
	either "Reserved" or “Intel Reserved”. The GMCH responds to accesses to
	“Reserved” address locations by completing the Host cycle. When a “Reserved”
	register location is Read, in certain cases, a zero value can be returned
	(“Reserved” registers can be 8-bit, 16-bit, or 32-bit in size) or a non-zero value can
	be returned. In certain cases, Writes to “Reserved” registers may have no effect on
	the GMCH or may cause system failure. Registers that are marked as “Intel
	Reserved” must not be modified by system software.
Default Value upon a	Upon Reset, the GMCH sets all of its internal configuration registers to
Reset	predetermined default states. Some register values at Reset are determined by
	external strapping options. The default state represents the minimum functionality
	feature set required to successfully bring up the system. Hence, it does not
	represent the optimal system configuration. It is the responsibility of the system
	initialization software (usually BIOS) to properly determine the DDR SDRAM
	configurations, operating parameters and optional system features that are
	applicable, and to program the GMCH registers accordingly.
S	SW Semaphore.

A physical PCI Bus #0 does not exist. The Hub interface and the internal devices in the GMCH and ICH4-M logically constitute PCI Bus #0 to configuration software.

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