D15343-003 159 | Intel guide

Ballout and Package Information

Row	Column	Signal Name		Row	Column	Signal Name		Row	Column	Signal Name

AG	22	SDQ[47]		AG	2	SDQS[0]		AC	21	SRAS#

AE	23	SDQ[48]		AH	5	SDQS[1]		AD	25	SWE#

AH	23	SDQ[49]		AH	8	SDQS[2]		W	21	VCC

AE	2	SDQ[5]		AE	12	SDQS[3]		AA	19	VCC

AE	24	SDQ[50]		AH	17	SDQS[4]		AA	17	VCC

AH	25	SDQ[51]		AE	21	SDQS[5]		T	17	VCC

AG	23	SDQ[52]		AH	24	SDQS[6]		P	17	VCC

AF	23	SDQ[53]		AH	27	SDQS[7]		U	16	VCC

AF	25	SDQ[54]		AD	15	SDQS[8]		R	16	VCC

AG	25	SDQ[55]		AC	18	SMA[0]		N	16	VCC

AH	26	SDQ[56]		AD	14	SMA[1]		AA	15	VCC

AE	26	SDQ[57]		AC	19	SMA[10]		T	15	VCC

AG	28	SDQ[58]		AD	5	SMA[11]		P	15	VCC

AF	28	SDQ[59]		AB	5	SMA[12]		J	15	VCC

AG	4	SDQ[6]		AD	13	SMA[2]		U	14	VCC

AG	26	SDQ[60]		AD	17	SMA[3]		R	14	VCC

AF	26	SDQ[61]		AD	11	SMA[4]		N	14	VCC

AE	27	SDQ[62]		AC	13	SMA[5]		H	14	VCC

AD	27	SDQ[63]		AD	8	SMA[6]		T	13	VCC

AG	14	RSVD		AD	7	SMA[7]		P	13	VCC

AE	14	RSVD		AC	6	SMA[8]		B	9	VCCADAC

AE	17	RSVD		AC	5	SMA[9]		A	9	VCCADAC

AG	16	RSVD		AD	16	SMAB[1]		A	6	VCCADPLLA

AH	14	RSVD		AC	12	SMAB[2]		B	16	VCCADPLLB

AE	15	RSVD		AF	11	SMAB[4]		Y	2	VCCAGPLL

AH	3	SDQ[7]		AD	10	SMAB[5]		D	29	VCCAHPLL

AF	16	RSVD		AB	1	SMRCOMP		A	11	VCCA

AF	17	RSVD		AJ	24	SMVREF_0		AF	1	VCCASM

AD	6	SDQ[8]		AJ	19	SMVSWINGH		AD	1	VCCASM

AG	5	SDQ[9]		AJ	22	SMVSWINGL		B	15	VCC1_5

D15343-003

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Image 159

Intel manual D15343-003 159

Contents

Intel 82854 Graphics Memory Controller Hub Gmch Datasheet D15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Date Revision Description Revision History Intel 82854 Graphics Memory Controller Hub Gmch Overview Processor/Host Bus SupportMemory System System Interrupts Video Stream DecoderVideo Overlay Display Internal Graphics Features Intel 82854 Graphics Memory Controller Hub Gmch Graphic Power Management Power ManagementHub Interface to ICH4-M Package Intel 854 Chipset system block diagram Native Graphic mode Terminology Terms and DescriptionsTerm Description ICH4-M Reference Documents Reference DocumentsDocument Location Intel 82854 Graphics Memory Controller Hub Gmch Intel 82854 Gmch System Architecture Technology Width Processor Host InterfaceGmch System Memory Interface DDR Sdram Memory Capacity Gmch Integrated DVO Ports Graphics FeaturesDisplay Features Gmch Analog Display Port Address Decode Policies Hub Interface Bytes MB/s Gmch ClockingIntel 82854 Gmch Interface Clocks Ratio System Interrupts Buffer Description Notation Description Host Interface Signal Descriptions Host Interface Signals HLOCK# DRDY#HIT# HITM# RS20# Response type RS20# SCAS# DDR Sdram InterfaceDDR Sdram Interface Descriptions SRAS# Hub Interface Signals Hub Interface Signals Clocks Drefclk Display Power Management Signaling This signal is used onlyDpms DAC Clocking Internal Graphics Display Signals Digital Video Output B Dvob Port Signal DescriptionsDigital Video Output B Dvob Port Digital Video Output C Dvoc Port Digital Video Output C Dvoc Port Signal Descriptions Dvob and Dvoc Port Common Signal Descriptions Analog CRT Display Signal DescriptionsAnalog CRT Display Gpio Signal Descriptions General Purpose Input/Output Signals Voltage References, PLL Power Voltage References, PLL Power Vcchl HlrcompPswing Hlvref Conceptual Overview of the Platform Configuration Structure Device Number AssignmentGmch Function Bus #0, Device# Nomenclature for Access Attributes Nomenclature for Access Attributes Standard PCI Bus Configuration Mechanism Routing Configuration AccessesPCI Bus #0 Configuration Mechanism Reserved Bits Primary PCI and Downstream Configuration MechanismDefault Value upon Reset Register Definitions I/O Mapped Registers Configaddress Configuration Address Register Reserved Bit Descriptions Configuration Data Register Configdata Configuration Data Register Name Function Read @ Write @ VGA I/O Mapped RegistersVGA I/O Mapped Register List Index Data Registers Gmch Configuration Space Device #0, Function#0 Register Name Default Value AccessEnd Attbase VID Vendor Identification Register Did Device Identification RegisterBit Descriptions 150 = Serr message is not generated by the Gmch for Device #0 Pcicmd PCI Command Register PCI Status Register Subc Sub Class Code Register RID Register Identification BCC Base Class Code Register HDR Header Type RegisterSvid Subsystem Vendor Identification Register Capptr Capabilities Pointer Register SID Subsystem Identification Register Capability ID Capid Capabilities Identification Register Device #0 VGA Rrbar Access Enable-R/WGMC Gmch Miscellaneous Control Register Device #0 MDA Present MDAP-R/W Reserved Device #2 Function #1 Enable/Disable GGC Gmch Graphics Control Register Device #0Bit Dafc Device and Function Control Register Device #0 Fdhc Fixed Dram Hold Control Register Device #0Bit Description 17 PAM60 Programmable Attribute Map Register Device #0 Attribute Bit AssignmentBits 7 Bits 6 Bits 5 Bits 4 Description Reserved PAM Registers Expansion Area C0000h-DFFFFh PAM Registers and Associated System Memory SegmentsDOS Application Area 00000h-9FFFh Video Buffer Area A0000h-BFFFFh Extended System Bios Area E0000h-EFFFFh System Bios Area F0000h-FFFFFhSmram System Management RAM Control Register Device #0 Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Bit Description Reserved Smicmd SMI Error Command Register Device #0 SCI on Gmch Thermal Sensor Trip Scicmd SCI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error SCI on Single-bit ECC Error Shic Secondary Host Interface Control Register Device #0 Reserved On Die Termination ODT Gating DisableReserved FSB Data Bus Power Management Control C2 state Gmch FSB Interface Power Management Control HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 Examples of usage DDR Internal Write to Read Command delay tWTRDDR Write Recovery time tWR DRT Dram Timing Register Device #0 Refresh Cycle Time tRFC Encoding CK between RD and WR commandsBack To Back Read-Read commands spacing DDR, different Rows Encoding CK between RD and RD commands Activate to Precharge delay tRAS, MAX Activate to Precharge delay tRAS, MINReserved CAS# Latency tCL Rcven DLL shutdown disable PCEn Page Close Enable TC Timer Control PDEn23CS# Signal Drive Control Dynamic Memory Interface Power Management Power State S1/S3 Refresh Control Ddim DDR Sdram Data Integrity Mode DRC Dram Controller Mode Register Device #0 011 000001 010 For Double Data Rate DTC Dram Throttling Control Register Device #0 Wttc DDR Sdram Throttle Mode Tmode 2724 High Priority Stream Throttling Enable Thermal Power Throttle Control fields Enable Hpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpll VCO Change Sequence Initiate Bit Hpllcc Hpll Clock Control Register Device #0 Rate Straps Read GFX CoreHPLLCC20 DVO Port CRT Port Regs Register Name Did Device Identification Register Device #2 VID Vendor Identification Register Device #2 Pcicmd PCI Command Register Device #2 RID Revision Identification Register Device #2 Pcists PCI Status Register Device #2 Base Class Code Basec 03=Display controller MLT Master Latency Timer Register Device #2CC Class Code Register Device #2 CLS Cache Line Size Register Device #2 Gmadr Graphics Memory Range Address Register Device #2 Bit Description Master Latency Timer Count Value ROPrefetchable Memory-RO Enable prefetching HDR Header Type Register Device #2 Memory / IO Space-RO Mmadr Memory Mapped Range Address Register Device #2Iobar I/O Base Address Register Device #2 Prefetchable Memory-RO Prevents prefetching Romadr Video Bios ROM Base Address Registers Device #2 Svid Subsystem Vendor Identification Register Device #2SID Subsystem Identification Register Device #2 Intrline Interrupt Line Register Device #2 Intrpin Interrupt Pin Register Device #2Mingnt Minimum Grant Register Device #2 Pmcap Power Management Capabilities Register Device #2 Auxiliary Power Source Hardwired toMaxlat Maximum Latency Register Device #2 Bits10 Power State Pmcs Power Management Control/Status Register Device #2 Simplified View of System Address Map System Memory Address Ranges Detailed View of System Address Map DOS Compatibility Area Compatible Smram Address Range 0A0000h-0BFFFFh System Memory Segments and Their AttributesDOS Area 000000h-09FFFFh Legacy VGA Ranges 0A0000h-0BFFFFh Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh Extended System Bios Area 0E0000h-0EFFFFhSystem Bios Area 0F0000h-0FFFFFh Extended System Memory Area Attributes Comments 1 15 MB-16 MB WindowPre-allocated System Memory Pre-allocated System Memory Dynamic Video Memory Technology Dvmt Extended Smram Address Range Hseg and TsegHseg Tseg PCI Memory Address Range Top of Main System Memory to 4 GB High Bios Area FFE00000h -FFFFFFFFh System Management Mode SMM Memory Range SMM Space RestrictionsSMM Space Definition System Memory Shadowing 5 I/O Address SpaceSMM Space Transaction Handling PCI I/O Address Mapping Gmch Decode Rules and Cross-Bridge Address Mapping Hub Interface Decode Rules Hub Interface Accesses to Gmch that Cross Device Boundaries Cycles Initiated Using PCI Protocol Accesses to Gmch that Cross Device BoundariesInterface Decode Rules Relation of DBI Bits to Data Bits Host Interface OverviewDynamic Bus Inversion System Bus Interrupt Delivery Upstream Interrupt Messages System Memory Organization and ConfigurationConfiguration Mechanism for DDR DIMMs System Memory Interface Byte Function DDR Sdram Performance DescriptionSystem Memory Register Programming Data Bytes on DDR Dimm Used for Programming Dram Registers 1 3D/2D Instruction Processing Integrated Graphics Overview 2.3 3D Primitives and Data Formats Support Setup Engine2 3D Engine Viewport Transform and Perspective Divide Perspective Correct Texture Support Backface CullingScan Converter Texture Engine Texture Chromakey Anti-AliasingTexture Map Filtering Bump Mapping Raster EngineMultiple Texture Composition Cubic Environment Mapping Color Dithering Texture Map BlendingCombining Intrinsic and Specular Color Components Color Shading Modes Alpha Blending Color Buffer Formats Destination AlphaDepth Buffer 4.1 256-Bit Pattern Fill and BLT Engine 4 2D EngineStencil Buffer Projective Textures Alpha Stretch BLT Hardware Cursor Plane Native Graphic Mode onlyDual Display Usage Model Native Graphic Mode only Planes and Engines Overlay Plane Dynamic Bob and Weave Color Control Sub-picture Support Video FunctionalityMPEG-2 Decoding Hardware Motion Compensation Pipe a Timing Generator Unit Internal Graphic Display Interface Arib Support 1.2 H, V timing signals for active and blank timing HSYNC/VSYNC Field Timing Parameters Blend Function Interlaced Video Field displayInterlace support for Plane a graphics Arib 960 X 540 support DVO Control Data Bits Interlace support for Video Overlay Window Timing Register Switching Analog Display Port Characteristics Integrated RamdacDDC Display Data Channel 146 D15343-003 Power and Thermal Management General Description of Acpi States General Description of Supported CPU States Internal Thermal Sensor OverviewHysteresis Operation Usage External Thermal Sensor Input Strapping Configuration Strapping Signals and ConfigurationPin Name Strap Description Configuration Type Buffer Type Intel 82854 Gmch Straps for Frequency/CPU Configuration GST20FSB Freq DDR Freq Gfx Freq Core Vcc Ballout and Package Information VCC/VSS Voltage Groups Voltage Levels and Ball Out for Voltage GroupsName Voltage Level Ball out Ballout Table Row Column Signal Name 156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View