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Intel D15343-003 manual Errcmd Error Command Register Device #0

Models: D15343-003

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Register Description

4.8.21ERRCMD – Error Command Register (Device #0)

Address Offset:	64-65h
Default Value:	0000h
Access:	Read/Write Clear
Size:	16 bits

This register enables various errors to generate a SERR Hub Interface Special cycle. Since the GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH4-M over Hub interface. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register.

Note: An error can generate one and only one Hub Interface Error Special cycle. It is software's responsibility to make sure that when an SERR error message is enabled for an error condition, SMI and SCI error messages are disabled for that same error condition.

Bit	Description

15:14	Reserved

13	SERR on FSB Strobe Glitch: When this bit is asserted, the GMCH will generate a HI SERR
	message when a glitch is detected on one of the FSB strobes.

12	Reserved

11	SERR on GMCH Thermal Sensor Event:
	1: The GMCH generates a SERR Hub Interface Special cycle on a Thermal Sensor Trip that
	requires an SERR. The SERR must not be enabled at the same time as the SMI/SCI for a
	Thermal Sensor Trip event.
	0: Software must write a 1 to clear this status bit.

10	Reserved

9	SERR on LOCK to non-DDR SDRAM Memory:
	1: The GMCH generates an SERR Hub Interface Special cycle when a CPU initiated LOCK
	transaction targeting non-DDR SDRAM Memory Space occurs.
	0: Reporting of this condition is disabled.

8	SERR on DDR SDRAM Refresh timeout:
	1: The GMCH generates an SERR Hub Interface Special cycle when a DDR SDRAM Refresh
	timeout occurs.
	0: Reporting of this condition is disabled.

7	SERR on DDR SDRAM Throttle Condition:
	1: The GMCH generates an SERR Hub Interface Special cycle when a DDR SDRAM Read or
	Write Throttle condition occurs.
	0: Reporting of this condition is disabled.

6	SERR on Receiving Target Abort on Hub Interface:
	1: The GMCH generates an SERR Hub Interface Special cycle when a GMCH originated Hub
	interface cycle is terminated with a Target Abort.
	0: Reporting of this condition is disabled.

D15343-003

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Image 67

Intel D15343-003 manual Errcmd Error Command Register Device #0

Contents

Intel 82854 Graphics Memory Controller Hub Gmch DatasheetD15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Date Revision Description Revision HistoryIntel 82854 Graphics Memory Controller Hub Gmch Processor/Host Bus Support OverviewMemory System Video Stream Decoder System InterruptsVideo Overlay Display Internal Graphics FeaturesIntel 82854 Graphics Memory Controller Hub Gmch Power Management Graphic Power ManagementHub Interface to ICH4-M Package Intel 854 Chipset system block diagram Native Graphic modeTerms and Descriptions TerminologyTerm Description ICH4-M Reference Documents Reference DocumentsDocument Location Intel 82854 Graphics Memory Controller Hub Gmch Intel 82854 Gmch System ArchitectureTechnology Width Processor Host InterfaceGmch System Memory Interface DDR Sdram Memory CapacityGmch Integrated DVO Ports Graphics FeaturesDisplay Features Gmch Analog Display PortAddress Decode Policies Hub InterfaceBytes MB/s Gmch ClockingIntel 82854 Gmch Interface Clocks RatioSystem Interrupts Buffer Description Notation DescriptionHost Interface Signal Descriptions Host Interface SignalsHLOCK# DRDY#HIT# HITM#RS20# Response type RS20#SCAS# DDR Sdram InterfaceDDR Sdram Interface Descriptions SRAS#Hub Interface Signals Hub Interface SignalsClocks Drefclk Display Power Management Signaling This signal is used onlyDpms DAC ClockingDigital Video Output B Dvob Port Signal Descriptions Internal Graphics Display SignalsDigital Video Output B Dvob Port Digital Video Output C Dvoc Port Digital Video Output C Dvoc Port Signal DescriptionsAnalog CRT Display Signal Descriptions Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Gpio Signal Descriptions General Purpose Input/Output SignalsVoltage References, PLL Power Voltage References, PLL PowerVcchl HlrcompPswing HlvrefDevice Number Assignment Conceptual Overview of the Platform Configuration StructureGmch Function Bus #0, Device# Nomenclature for Access Attributes Nomenclature for Access AttributesRouting Configuration Accesses Standard PCI Bus Configuration MechanismPCI Bus #0 Configuration Mechanism Reserved Bits Primary PCI and Downstream Configuration MechanismDefault Value upon Reset Register DefinitionsI/O Mapped Registers Configaddress Configuration Address RegisterReserved Bit DescriptionsConfiguration Data Register Configdata Configuration Data RegisterName Function Read @ Write @ VGA I/O Mapped RegistersVGA I/O Mapped Register List Index Data RegistersRegister Name Default Value Access Gmch Configuration Space Device #0, Function#0End Attbase Did Device Identification Register VID Vendor Identification RegisterBit Descriptions 150 = Serr message is not generated by the Gmch for Device #0 Pcicmd PCI Command RegisterPCI Status Register Subc Sub Class Code Register RID Register IdentificationHDR Header Type Register BCC Base Class Code RegisterSvid Subsystem Vendor Identification Register Capptr Capabilities Pointer Register SID Subsystem Identification RegisterCapability ID Capid Capabilities Identification Register Device #0VGA Rrbar Access Enable-R/WGMC Gmch Miscellaneous Control Register Device #0 MDA Present MDAP-R/WGGC Gmch Graphics Control Register Device #0 Reserved Device #2 Function #1 Enable/DisableBit Fdhc Fixed Dram Hold Control Register Device #0 Dafc Device and Function Control Register Device #0Bit Description Attribute Bit Assignment 17 PAM60 Programmable Attribute Map Register Device #0Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved PAM Registers Expansion Area C0000h-DFFFFh PAM Registers and Associated System Memory SegmentsDOS Application Area 00000h-9FFFh Video Buffer Area A0000h-BFFFFhSystem Bios Area F0000h-FFFFFh Extended System Bios Area E0000h-EFFFFhSmram System Management RAM Control Register Device #0 Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Bit Description Reserved Smicmd SMI Error Command Register Device #0SCI on Gmch Thermal Sensor Trip Scicmd SCI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error SCI on Single-bit ECC ErrorShic Secondary Host Interface Control Register Device #0 Reserved On Die Termination ODT Gating DisableReserved FSB Data Bus Power Management Control C2 state Gmch FSB Interface Power Management ControlHEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 Examples of usage DDR Internal Write to Read Command delay tWTRDDR Write Recovery time tWR DRT Dram Timing Register Device #0Refresh Cycle Time tRFC Encoding CK between RD and WR commandsBack To Back Read-Read commands spacing DDR, different Rows Encoding CK between RD and RD commandsActivate to Precharge delay tRAS, MIN Activate to Precharge delay tRAS, MAXReserved CAS# Latency tCL Rcven DLL shutdown disable PCEn Page Close Enable TC Timer Control PDEn23CS# Signal Drive Control Dynamic Memory Interface Power ManagementPower State S1/S3 Refresh Control Ddim DDR Sdram Data Integrity Mode DRC Dram Controller Mode Register Device #0011 000001 010For Double Data Rate DTC Dram Throttling Control Register Device #0 Wttc DDR Sdram Throttle Mode Tmode2724 High Priority Stream Throttling Enable Thermal Power Throttle Control fields EnableHpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpll VCO Change Sequence Initiate Bit Hpllcc Hpll Clock Control Register Device #0Rate Straps Read GFX CoreHPLLCC20 DVO Port CRT PortRegs Register NameDid Device Identification Register Device #2 VID Vendor Identification Register Device #2Pcicmd PCI Command Register Device #2 RID Revision Identification Register Device #2 Pcists PCI Status Register Device #2Base Class Code Basec 03=Display controller MLT Master Latency Timer Register Device #2CC Class Code Register Device #2 CLS Cache Line Size Register Device #2Gmadr Graphics Memory Range Address Register Device #2 Bit Description Master Latency Timer Count Value ROPrefetchable Memory-RO Enable prefetching HDR Header Type Register Device #2Memory / IO Space-RO Mmadr Memory Mapped Range Address Register Device #2Iobar I/O Base Address Register Device #2 Prefetchable Memory-RO Prevents prefetchingSvid Subsystem Vendor Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2SID Subsystem Identification Register Device #2 Intrpin Interrupt Pin Register Device #2 Intrline Interrupt Line Register Device #2Mingnt Minimum Grant Register Device #2 Auxiliary Power Source Hardwired to Pmcap Power Management Capabilities Register Device #2Maxlat Maximum Latency Register Device #2 Bits10 Power State Pmcs Power Management Control/Status Register Device #2Simplified View of System Address Map System Memory Address RangesDetailed View of System Address Map DOS Compatibility AreaCompatible Smram Address Range 0A0000h-0BFFFFh System Memory Segments and Their AttributesDOS Area 000000h-09FFFFh Legacy VGA Ranges 0A0000h-0BFFFFhMonochrome Display Adapter MDA Range 0B0000h 0B7FFFh Extended System Bios Area 0E0000h-0EFFFFhSystem Bios Area 0F0000h-0FFFFFh Extended System Memory AreaAttributes Comments 1 15 MB-16 MB WindowPre-allocated System Memory Pre-allocated System MemoryDynamic Video Memory Technology Dvmt Extended Smram Address Range Hseg and TsegHseg TsegPCI Memory Address Range Top of Main System Memory to 4 GB High Bios Area FFE00000h -FFFFFFFFhSMM Space Restrictions System Management Mode SMM Memory RangeSMM Space Definition 5 I/O Address Space System Memory ShadowingSMM Space Transaction Handling PCI I/O Address Mapping Gmch Decode Rules and Cross-Bridge Address MappingHub Interface Decode Rules Hub Interface Accesses to Gmch that Cross Device BoundariesAccesses to Gmch that Cross Device Boundaries Cycles Initiated Using PCI ProtocolInterface Decode Rules Relation of DBI Bits to Data Bits Host Interface OverviewDynamic Bus Inversion System Bus Interrupt DeliveryUpstream Interrupt Messages System Memory Organization and ConfigurationConfiguration Mechanism for DDR DIMMs System Memory InterfaceByte Function DDR Sdram Performance DescriptionSystem Memory Register Programming Data Bytes on DDR Dimm Used for Programming Dram Registers1 3D/2D Instruction Processing Integrated Graphics Overview2.3 3D Primitives and Data Formats Support Setup Engine2 3D Engine Viewport Transform and Perspective DividePerspective Correct Texture Support Backface CullingScan Converter Texture EngineAnti-Aliasing Texture ChromakeyTexture Map Filtering Bump Mapping Raster EngineMultiple Texture Composition Cubic Environment MappingColor Dithering Texture Map BlendingCombining Intrinsic and Specular Color Components Color Shading ModesColor Buffer Formats Destination Alpha Alpha BlendingDepth Buffer 4.1 256-Bit Pattern Fill and BLT Engine 4 2D EngineStencil Buffer Projective TexturesAlpha Stretch BLT Hardware Cursor Plane Native Graphic Mode onlyDual Display Usage Model Native Graphic Mode only Planes and EnginesOverlay Plane Dynamic Bob and Weave Color ControlSub-picture Support Video FunctionalityMPEG-2 Decoding Hardware Motion CompensationPipe a Timing Generator Unit Internal Graphic Display InterfaceArib Support 1.2 H, V timing signals for active and blank timingHSYNC/VSYNC Field Timing ParametersInterlaced Video Field display Blend FunctionInterlace support for Plane a graphics Arib 960 X 540 support DVO Control Data Bits Interlace support for Video Overlay WindowTiming Register Switching Integrated Ramdac Analog Display Port CharacteristicsDDC Display Data Channel 146 D15343-003 Power and Thermal Management General Description of Acpi States General Description of Supported CPU StatesOverview Internal Thermal SensorHysteresis Operation Usage External Thermal Sensor InputStrapping Signals and Configuration Strapping ConfigurationPin Name Strap Description Configuration Type Buffer Type GST20 Intel 82854 Gmch Straps for Frequency/CPU ConfigurationFSB Freq DDR Freq Gfx Freq Core Vcc Ballout and Package Information Voltage Levels and Ball Out for Voltage Groups VCC/VSS Voltage GroupsName Voltage Level Ball out Ballout Table Row Column Signal Name156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Top ViewIntel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View