CC Class Code Register Device #2 | Intel D15343-003 guide

Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.11.6CC – Class Code Register (Device #2)

Address Offset:	09-0Bh
Default Value:	030000h
Access:	Read Only
Size:	24 bits

This register contains the device programming interface information related to the Sub-Class code and Base Class code definition for the IGD. This register also contains the Base Class code and the function sub-class in relation to the Base Class code.

Bit	Description

23:16	Base Class Code (BASEC): 03=Display controller

15:8	Sub-Class Code (SCC):
	Function 0: 00h=VGA compatible or 80h=Non VGA
	Function 1: 80h=Non VGA

7:0	Programming Interface (PI): 00h=Hardwired as a Display controller.

4.11.7CLS – Cache Line Size Register (Device #2)

Address Offset:	0Ch
Default Value:	00h
Access:	Read Only
Size:	8 bits

The IGD does not support this register as a PCI slave.

Bit	Description

7:0	Cache Line Size (CLS) – RO

4.11.8MLT – Master Latency Timer Register (Device #2)

Address Offset:	0Dh
Default Value:	00h
Access:	Read Only
Size:	8 bits

The IGD does not support the programmability of the master latency timer because it does not perform bursts.

104	D15343-003

Image 104

Intel D15343-003 manual CC Class Code Register Device #2, CLS Cache Line Size Register Device #2

Contents

Datasheet Intel 82854 Graphics Memory Controller Hub Gmch D15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Revision History Date Revision Description Intel 82854 Graphics Memory Controller Hub Gmch Memory System OverviewProcessor/Host Bus Support Video Overlay System InterruptsVideo Stream Decoder Internal Graphics Features Display Intel 82854 Graphics Memory Controller Hub Gmch Hub Interface to ICH4-M Graphic Power ManagementPower Management Intel 854 Chipset system block diagram Native Graphic mode Package Term Description TerminologyTerms and Descriptions ICH4-M Document Location Reference DocumentsReference Documents Intel 82854 Graphics Memory Controller Hub Gmch System Architecture Intel 82854 Gmch Processor Host Interface Gmch System Memory InterfaceDDR Sdram Memory Capacity Technology Width Graphics Features Display FeaturesGmch Analog Display Port Gmch Integrated DVO Ports Hub Interface Address Decode Policies Gmch Clocking Intel 82854 Gmch Interface ClocksRatio Bytes MB/s System Interrupts Notation Description Buffer Description Host Interface Signals Host Interface Signal Descriptions DRDY# HIT#HITM# HLOCK# RS20# RS20# Response type DDR Sdram Interface DDR Sdram Interface DescriptionsSRAS# SCAS# Hub Interface Signals Hub Interface Signals Clocks Display Power Management Signaling This signal is used only DpmsDAC Clocking Drefclk Digital Video Output B Dvob Port Internal Graphics Display SignalsDigital Video Output B Dvob Port Signal Descriptions Digital Video Output C Dvoc Port Signal Descriptions Digital Video Output C Dvoc Port Analog CRT Display Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Signal Descriptions General Purpose Input/Output Signals Gpio Signal Descriptions Voltage References, PLL Power Voltage References, PLL Power Hlrcomp PswingHlvref Vcchl Gmch Function Bus #0, Device# Conceptual Overview of the Platform Configuration StructureDevice Number Assignment Nomenclature for Access Attributes Nomenclature for Access Attributes PCI Bus #0 Configuration Mechanism Standard PCI Bus Configuration MechanismRouting Configuration Accesses Primary PCI and Downstream Configuration Mechanism Default Value upon ResetRegister Definitions Reserved Bits Configaddress Configuration Address Register I/O Mapped Registers Bit Descriptions Reserved Configdata Configuration Data Register Configuration Data Register VGA I/O Mapped Registers VGA I/O Mapped Register ListIndex Data Registers Name Function Read @ Write @ End Gmch Configuration Space Device #0, Function#0Register Name Default Value Access Attbase Bit Descriptions 150 VID Vendor Identification RegisterDid Device Identification Register Pcicmd PCI Command Register = Serr message is not generated by the Gmch for Device #0 PCI Status Register RID Register Identification Subc Sub Class Code Register Svid Subsystem Vendor Identification Register BCC Base Class Code RegisterHDR Header Type Register SID Subsystem Identification Register Capptr Capabilities Pointer Register Capid Capabilities Identification Register Device #0 Capability ID Rrbar Access Enable-R/W GMC Gmch Miscellaneous Control Register Device #0MDA Present MDAP-R/W VGA Bit Reserved Device #2 Function #1 Enable/DisableGGC Gmch Graphics Control Register Device #0 Bit Description Dafc Device and Function Control Register Device #0Fdhc Fixed Dram Hold Control Register Device #0 Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved 17 PAM60 Programmable Attribute Map Register Device #0Attribute Bit Assignment PAM Registers PAM Registers and Associated System Memory Segments DOS Application Area 00000h-9FFFhVideo Buffer Area A0000h-BFFFFh Expansion Area C0000h-DFFFFh Smram System Management RAM Control Register Device #0 Extended System Bios Area E0000h-EFFFFhSystem Bios Area F0000h-FFFFFh Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Smicmd SMI Error Command Register Device #0 Bit Description Reserved Scicmd SCI Error Command Register Device #0 Reserved SCI on Multiple-bit ECC ErrorSCI on Single-bit ECC Error SCI on Gmch Thermal Sensor Trip Reserved On Die Termination ODT Gating Disable Reserved FSB Data Bus Power Management ControlC2 state Gmch FSB Interface Power Management Control Shic Secondary Host Interface Control Register Device #0 HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DDR Internal Write to Read Command delay tWTR DDR Write Recovery time tWRDRT Dram Timing Register Device #0 Examples of usage Encoding CK between RD and WR commands Back To Back Read-Read commands spacing DDR, different RowsEncoding CK between RD and RD commands Refresh Cycle Time tRFC Reserved CAS# Latency tCL Activate to Precharge delay tRAS, MAXActivate to Precharge delay tRAS, MIN PCEn Page Close Enable TC Timer Control PDEn23 CS# Signal Drive ControlDynamic Memory Interface Power Management Rcven DLL shutdown disable Power State S1/S3 Refresh Control DRC Dram Controller Mode Register Device #0 Ddim DDR Sdram Data Integrity Mode 000 001010 011 For Double Data Rate DTC Dram Throttling Control Register Device #0 DDR Sdram Throttle Mode Tmode Wttc 2724 Thermal Power Throttle Control fields Enable High Priority Stream Throttling Enable Hpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpllcc Hpll Clock Control Register Device #0 Hpll VCO Change Sequence Initiate Bit Straps Read GFX Core HPLLCC20DVO Port CRT Port Rate Register Name Regs VID Vendor Identification Register Device #2 Did Device Identification Register Device #2 Pcicmd PCI Command Register Device #2 Pcists PCI Status Register Device #2 RID Revision Identification Register Device #2 MLT Master Latency Timer Register Device #2 CC Class Code Register Device #2CLS Cache Line Size Register Device #2 Base Class Code Basec 03=Display controller Bit Description Master Latency Timer Count Value RO Prefetchable Memory-RO Enable prefetchingHDR Header Type Register Device #2 Gmadr Graphics Memory Range Address Register Device #2 Mmadr Memory Mapped Range Address Register Device #2 Iobar I/O Base Address Register Device #2Prefetchable Memory-RO Prevents prefetching Memory / IO Space-RO SID Subsystem Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2Svid Subsystem Vendor Identification Register Device #2 Mingnt Minimum Grant Register Device #2 Intrline Interrupt Line Register Device #2Intrpin Interrupt Pin Register Device #2 Maxlat Maximum Latency Register Device #2 Pmcap Power Management Capabilities Register Device #2Auxiliary Power Source Hardwired to Pmcs Power Management Control/Status Register Device #2 Bits10 Power State System Memory Address Ranges Simplified View of System Address Map DOS Compatibility Area Detailed View of System Address Map System Memory Segments and Their Attributes DOS Area 000000h-09FFFFhLegacy VGA Ranges 0A0000h-0BFFFFh Compatible Smram Address Range 0A0000h-0BFFFFh Extended System Bios Area 0E0000h-0EFFFFh System Bios Area 0F0000h-0FFFFFhExtended System Memory Area Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh 1 15 MB-16 MB Window Pre-allocated System MemoryPre-allocated System Memory Attributes Comments Extended Smram Address Range Hseg and Tseg HsegTseg Dynamic Video Memory Technology Dvmt High Bios Area FFE00000h -FFFFFFFFh PCI Memory Address Range Top of Main System Memory to 4 GB SMM Space Definition System Management Mode SMM Memory RangeSMM Space Restrictions SMM Space Transaction Handling System Memory Shadowing5 I/O Address Space Gmch Decode Rules and Cross-Bridge Address Mapping PCI I/O Address Mapping Hub Interface Accesses to Gmch that Cross Device Boundaries Hub Interface Decode Rules Interface Decode Rules Cycles Initiated Using PCI ProtocolAccesses to Gmch that Cross Device Boundaries Host Interface Overview Dynamic Bus InversionSystem Bus Interrupt Delivery Relation of DBI Bits to Data Bits System Memory Organization and Configuration Configuration Mechanism for DDR DIMMsSystem Memory Interface Upstream Interrupt Messages DDR Sdram Performance Description System Memory Register ProgrammingData Bytes on DDR Dimm Used for Programming Dram Registers Byte Function Integrated Graphics Overview 1 3D/2D Instruction Processing Setup Engine 2 3D EngineViewport Transform and Perspective Divide 2.3 3D Primitives and Data Formats Support Backface Culling Scan ConverterTexture Engine Perspective Correct Texture Support Texture Map Filtering Texture ChromakeyAnti-Aliasing Raster Engine Multiple Texture CompositionCubic Environment Mapping Bump Mapping Texture Map Blending Combining Intrinsic and Specular Color ComponentsColor Shading Modes Color Dithering Depth Buffer Alpha BlendingColor Buffer Formats Destination Alpha 4 2D Engine Stencil BufferProjective Textures 4.1 256-Bit Pattern Fill and BLT Engine Hardware Cursor Plane Native Graphic Mode only Dual Display Usage Model Native Graphic Mode onlyPlanes and Engines Alpha Stretch BLT Overlay Plane Color Control Dynamic Bob and Weave Video Functionality MPEG-2 DecodingHardware Motion Compensation Sub-picture Support Internal Graphic Display Interface Pipe a Timing Generator Unit 1.2 H, V timing signals for active and blank timing Arib Support Parameters HSYNC/VSYNC Field Timing Interlace support for Plane a graphics Blend FunctionInterlaced Video Field display Arib 960 X 540 support Interlace support for Video Overlay Window DVO Control Data Bits Timing Register Switching DDC Display Data Channel Analog Display Port CharacteristicsIntegrated Ramdac 146 D15343-003 Power and Thermal Management General Description of Supported CPU States General Description of Acpi States Hysteresis Operation Internal Thermal SensorOverview External Thermal Sensor Input Usage Pin Name Strap Description Configuration Type Buffer Type Strapping ConfigurationStrapping Signals and Configuration FSB Freq DDR Freq Gfx Freq Core Vcc Intel 82854 Gmch Straps for Frequency/CPU ConfigurationGST20 Ballout and Package Information Name Voltage Level Ball out VCC/VSS Voltage GroupsVoltage Levels and Ball Out for Voltage Groups Row Column Signal Name Ballout Table 156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View