Datasheet
Intel 82854 Graphics Memory Controller Hub Gmch
D15343-003
Contents
Intel 82854 Graphics Memory Controller Hub Gmch
10.9
127
Figures
152
Revision History
Date Revision Description
Intel 82854 Graphics Memory Controller Hub Gmch
Overview
Processor/Host Bus Support
Memory System
System Interrupts
Video Stream Decoder
Video Overlay
Internal Graphics Features
Display
Intel 82854 Graphics Memory Controller Hub Gmch
Graphic Power Management
Power Management
Hub Interface to ICH4-M
Intel 854 Chipset system block diagram Native Graphic mode
Package
Terminology
Terms and Descriptions
Term Description
ICH4-M
Reference Documents
Reference Documents
Document Location
Intel 82854 Graphics Memory Controller Hub Gmch
System Architecture
Intel 82854 Gmch
DDR Sdram Memory Capacity
Processor Host Interface
Gmch System Memory Interface
Technology Width
Gmch Analog Display Port
Graphics Features
Display Features
Gmch Integrated DVO Ports
Hub Interface
Address Decode Policies
Ratio
Gmch Clocking
Intel 82854 Gmch Interface Clocks
Bytes MB/s
System Interrupts
Notation Description
Buffer Description
Host Interface Signals
Host Interface Signal Descriptions
HITM#
DRDY#
HIT#
HLOCK#
RS20#
RS20# Response type
SRAS#
DDR Sdram Interface
DDR Sdram Interface Descriptions
SCAS#
Hub Interface Signals
Hub Interface Signals
Clocks
DAC Clocking
Display Power Management Signaling This signal is used only
Dpms
Drefclk
Internal Graphics Display Signals
Digital Video Output B Dvob Port Signal Descriptions
Digital Video Output B Dvob Port
Digital Video Output C Dvoc Port Signal Descriptions
Digital Video Output C Dvoc Port
Dvob and Dvoc Port Common Signal Descriptions
Analog CRT Display Signal Descriptions
Analog CRT Display
General Purpose Input/Output Signals
Gpio Signal Descriptions
Voltage References, PLL Power
Voltage References, PLL Power
Hlvref
Hlrcomp
Pswing
Vcchl
Conceptual Overview of the Platform Configuration Structure
Device Number Assignment
Gmch Function Bus #0, Device#
Nomenclature for Access Attributes
Nomenclature for Access Attributes
Standard PCI Bus Configuration Mechanism
Routing Configuration Accesses
PCI Bus #0 Configuration Mechanism
Register Definitions
Primary PCI and Downstream Configuration Mechanism
Default Value upon Reset
Reserved Bits
Configaddress Configuration Address Register
I/O Mapped Registers
Bit Descriptions
Reserved
Configdata Configuration Data Register
Configuration Data Register
Index Data Registers
VGA I/O Mapped Registers
VGA I/O Mapped Register List
Name Function Read @ Write @
Gmch Configuration Space Device #0, Function#0
Register Name Default Value Access
End
Attbase
VID Vendor Identification Register
Did Device Identification Register
Bit Descriptions 150
Pcicmd PCI Command Register
= Serr message is not generated by the Gmch for Device #0
PCI Status Register
RID Register Identification
Subc Sub Class Code Register
BCC Base Class Code Register
HDR Header Type Register
Svid Subsystem Vendor Identification Register
SID Subsystem Identification Register
Capptr Capabilities Pointer Register
Capid Capabilities Identification Register Device #0
Capability ID
MDA Present MDAP-R/W
Rrbar Access Enable-R/W
GMC Gmch Miscellaneous Control Register Device #0
VGA
Reserved Device #2 Function #1 Enable/Disable
GGC Gmch Graphics Control Register Device #0
Bit
Dafc Device and Function Control Register Device #0
Fdhc Fixed Dram Hold Control Register Device #0
Bit Description
17 PAM60 Programmable Attribute Map Register Device #0
Attribute Bit Assignment
Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved
PAM Registers
Video Buffer Area A0000h-BFFFFh
PAM Registers and Associated System Memory Segments
DOS Application Area 00000h-9FFFh
Expansion Area C0000h-DFFFFh
Extended System Bios Area E0000h-EFFFFh
System Bios Area F0000h-FFFFFh
Smram System Management RAM Control Register Device #0
Esmramc Extended System Management RAM Control Device #0
Errsts Error Status Register Device #0
Errcmd Error Command Register Device #0
Smicmd SMI Error Command Register Device #0
Bit Description Reserved
SCI on Single-bit ECC Error
Scicmd SCI Error Command Register Device #0
Reserved SCI on Multiple-bit ECC Error
SCI on Gmch Thermal Sensor Trip
C2 state Gmch FSB Interface Power Management Control
Reserved On Die Termination ODT Gating Disable
Reserved FSB Data Bus Power Management Control
Shic Secondary Host Interface Control Register Device #0
HEM Host Error Control, Status, and Observation Device #0
DRB
VID Vendor Identification Register
Pcicmd PCI Command Register
Pcists PCI Status Register
RID Revision Identification Register
Device. Reads and Writes to this location have no effect
DRB Dram Row 03 Boundary Register Device #0
DRA Dram Row Attribute Register Device #0
DRT Dram Timing Register Device #0
DDR Internal Write to Read Command delay tWTR
DDR Write Recovery time tWR
Examples of usage
Encoding CK between RD and RD commands
Encoding CK between RD and WR commands
Back To Back Read-Read commands spacing DDR, different Rows
Refresh Cycle Time tRFC
Activate to Precharge delay tRAS, MAX
Activate to Precharge delay tRAS, MIN
Reserved CAS# Latency tCL
Dynamic Memory Interface Power Management
PCEn Page Close Enable TC Timer Control PDEn23
CS# Signal Drive Control
Rcven DLL shutdown disable
Power State S1/S3 Refresh Control
DRC Dram Controller Mode Register Device #0
Ddim DDR Sdram Data Integrity Mode
010
000
001
011
For Double Data Rate
DTC Dram Throttling Control Register Device #0
DDR Sdram Throttle Mode Tmode
Wttc
2724
Thermal Power Throttle Control fields Enable
High Priority Stream Throttling Enable
Hpllcc
Did Device Identification Register
Pcicmd PCI Command Register
Pcists PCI Status Register
Subc Sub-Class Code Register
ID Subsystem Identification Register
Hpllcc Hpll Clock Control Register Device #0
Hpll VCO Change Sequence Initiate Bit
DVO Port CRT Port
Straps Read GFX Core
HPLLCC20
Rate
Register Name
Regs
VID Vendor Identification Register Device #2
Did Device Identification Register Device #2
Pcicmd PCI Command Register Device #2
Pcists PCI Status Register Device #2
RID Revision Identification Register Device #2
CLS Cache Line Size Register Device #2
MLT Master Latency Timer Register Device #2
CC Class Code Register Device #2
Base Class Code Basec 03=Display controller
HDR Header Type Register Device #2
Bit Description Master Latency Timer Count Value RO
Prefetchable Memory-RO Enable prefetching
Gmadr Graphics Memory Range Address Register Device #2
Prefetchable Memory-RO Prevents prefetching
Mmadr Memory Mapped Range Address Register Device #2
Iobar I/O Base Address Register Device #2
Memory / IO Space-RO
Romadr Video Bios ROM Base Address Registers Device #2
Svid Subsystem Vendor Identification Register Device #2
SID Subsystem Identification Register Device #2
Intrline Interrupt Line Register Device #2
Intrpin Interrupt Pin Register Device #2
Mingnt Minimum Grant Register Device #2
Pmcap Power Management Capabilities Register Device #2
Auxiliary Power Source Hardwired to
Maxlat Maximum Latency Register Device #2
Pmcs Power Management Control/Status Register Device #2
Bits10 Power State
System Memory Address Ranges
Simplified View of System Address Map
DOS Compatibility Area
Detailed View of System Address Map
Legacy VGA Ranges 0A0000h-0BFFFFh
System Memory Segments and Their Attributes
DOS Area 000000h-09FFFFh
Compatible Smram Address Range 0A0000h-0BFFFFh
Extended System Memory Area
Extended System Bios Area 0E0000h-0EFFFFh
System Bios Area 0F0000h-0FFFFFh
Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh
Pre-allocated System Memory
1 15 MB-16 MB Window
Pre-allocated System Memory
Attributes Comments
Tseg
Extended Smram Address Range Hseg and Tseg
Hseg
Dynamic Video Memory Technology Dvmt
High Bios Area FFE00000h -FFFFFFFFh
PCI Memory Address Range Top of Main System Memory to 4 GB
System Management Mode SMM Memory Range
SMM Space Restrictions
SMM Space Definition
System Memory Shadowing
5 I/O Address Space
SMM Space Transaction Handling
Gmch Decode Rules and Cross-Bridge Address Mapping
PCI I/O Address Mapping
Hub Interface Accesses to Gmch that Cross Device Boundaries
Hub Interface Decode Rules
Cycles Initiated Using PCI Protocol
Accesses to Gmch that Cross Device Boundaries
Interface Decode Rules
System Bus Interrupt Delivery
Host Interface Overview
Dynamic Bus Inversion
Relation of DBI Bits to Data Bits
System Memory Interface
System Memory Organization and Configuration
Configuration Mechanism for DDR DIMMs
Upstream Interrupt Messages
Data Bytes on DDR Dimm Used for Programming Dram Registers
DDR Sdram Performance Description
System Memory Register Programming
Byte Function
Integrated Graphics Overview
1 3D/2D Instruction Processing
Viewport Transform and Perspective Divide
Setup Engine
2 3D Engine
2.3 3D Primitives and Data Formats Support
Texture Engine
Backface Culling
Scan Converter
Perspective Correct Texture Support
Texture Chromakey
Anti-Aliasing
Texture Map Filtering
Cubic Environment Mapping
Raster Engine
Multiple Texture Composition
Bump Mapping
Color Shading Modes
Texture Map Blending
Combining Intrinsic and Specular Color Components
Color Dithering
Alpha Blending
Color Buffer Formats Destination Alpha
Depth Buffer
Projective Textures
4 2D Engine
Stencil Buffer
4.1 256-Bit Pattern Fill and BLT Engine
Planes and Engines
Hardware Cursor Plane Native Graphic Mode only
Dual Display Usage Model Native Graphic Mode only
Alpha Stretch BLT
Overlay Plane
Color Control
Dynamic Bob and Weave
Hardware Motion Compensation
Video Functionality
MPEG-2 Decoding
Sub-picture Support
Internal Graphic Display Interface
Pipe a Timing Generator Unit
1.2 H, V timing signals for active and blank timing
Arib Support
Parameters
HSYNC/VSYNC Field Timing
Blend Function
Interlaced Video Field display
Interlace support for Plane a graphics
Arib 960 X 540 support
Interlace support for Video Overlay Window
DVO Control Data Bits
Timing Register Switching
Analog Display Port Characteristics
Integrated Ramdac
DDC Display Data Channel
146 D15343-003
Power and Thermal Management
General Description of Supported CPU States
General Description of Acpi States
Internal Thermal Sensor
Overview
Hysteresis Operation
External Thermal Sensor Input
Usage
Strapping Configuration
Strapping Signals and Configuration
Pin Name Strap Description Configuration Type Buffer Type
Intel 82854 Gmch Straps for Frequency/CPU Configuration
GST20
FSB Freq DDR Freq Gfx Freq Core Vcc
Ballout and Package Information
VCC/VSS Voltage Groups
Voltage Levels and Ball Out for Voltage Groups
Name Voltage Level Ball out
Row Column Signal Name
Ballout Table
156 D15343-003
D15343-003 157
158 D15343-003
D15343-003 159
160 D15343-003
D15343-003 161
162 D15343-003
D15343-003 163
Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View
Package Mechanical Information
Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View
Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View