Intel D15343-003 manual Mmadr Memory Mapped Range Address Register Device #2, Memory / IO Space-RO

Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.11.11MMADR – Memory Mapped Range Address Register (Device #2)

Address Offset:	14-17h
Default Value:	00000000h
Access:	Read/Write, Read Only
Size:	32 bits

This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by bits [31:19].

Bit	Description
31:19	Memory Base Address–R/W:Set by the OS, these bits correspond to address signals [31:19].
18:4	Address Mask–RO:Indicate 512-kB address range.
3	Prefetchable Memory–RO: Prevents prefetching.
2:1	Memory Type–RO:Indicates 32-bit address.
0	Memory / IO Space–RO:Indicates System Memory space.

4.11.12IOBAR – I/O Base Address Register (Device #2)

Address Offset:	18-1Bh
Default Value:	00000001h
Access:	Read/Write
Size:	32 bits

This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 are programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1 are fixed and return zero, bit 0 is hardwired to a one indicating that 8-bytes of I/O space are decoded.

Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if internal graphics is disabled. Note that access to this IO BAR is independent of VGA functionality within Device #2. Also note that this mechanism is available only through Function #0 of Device#2 and is not duplicated in Function #1.

If accesses to this I/O bar are allowed, then the GMCH claims all 8-bit, 16-bit, or 32-bit I/O cycles from the CPU that falls within the 8B claimed.

Bit	Description
31:16	Reserved
15:3	IO Base Address–R/W:Set by the OS, these bits correspond to address signals [15:3].
2:1	Memory Type–RO:Indicates 32-bit address.

0Memory / IO Space–RO

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