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Intel D15343-003 Encoding CK between RD and WR commands, Encoding CK between RD and RD commands

Models: D15343-003

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			Register Description

27:26	Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This
	field determines the RD-WR command spacing, in terms of common clocks based on the following
	formula: CL + 0.5xBL + TA (RD-WR) – DQSS
	DQSS: is time from Write command to data and is always 1 CK
	BL: is Burst Length which is set to 4
	TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK
	CL: is CAS latency, can be set to 2 or 2.5
	Examples of usage:
	For BL=4, with single DQ turn-around and CL=2, this field must be set to 4 CK (2+2+1-1)
	Encoding	CK between RD and WR commands
	00:		7
	01:		6
	10:		5
	11:		4
	NOTE: Since reads in DDR SDRAM cannot be terminated by Writes, the Space between
	commands is not a function of Cycle Length but of Burst Length.

25	Back To Back Read-Read commands spacing (DDR, different Rows):
	This field determines the RD-RD Command Spacing, in terms of common clocks based on the
	following formula: 0.5xBL + TA(RD-RD)
	BL: is Burst Length and can be set to 4.
	TA (RD-RD): is required DQ turn-around, can be set to 1 or 2 CK
	Examples of usage:
	For BL=4, with single DQ turn-around, this field must be set to 3 CK (2+1)
	Encoding	CK between RD and RD commands
	0:		4
	1:		3
	NOTE: Since a Read to a different row does not terminate a Read, the Space between commands
	is not a function of Cycle Length but of Burst Length.

24:15	Reserved

14:12	Refresh Cycle Time (tRFC):
	Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until
	following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR
	SDRAM.
	Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this
	field will be set to 8 clocks for DDR200, 10 clocks for DDR266.
	Encoding	tRFC
	000:	14	clocks
	001:	13	clocks
	010:	12	clocks
	011:	11	clocks
	100:	10	clocks
	101:	9	clocks
	110:	8	clocks
	111:	7	clocks

D15343-003

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Image 81

Intel D15343-003 manual Encoding CK between RD and WR commands, Back To Back Read-Read commands spacing DDR, different Rows

Contents

Intel 82854 Graphics Memory Controller Hub Gmch DatasheetD15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Date Revision Description Revision HistoryIntel 82854 Graphics Memory Controller Hub Gmch Overview Processor/Host Bus SupportMemory System System Interrupts Video Stream DecoderVideo Overlay Display Internal Graphics FeaturesIntel 82854 Graphics Memory Controller Hub Gmch Graphic Power Management Power ManagementHub Interface to ICH4-M Package Intel 854 Chipset system block diagram Native Graphic modeTerminology Terms and DescriptionsTerm Description ICH4-M Reference Documents Reference DocumentsDocument Location Intel 82854 Graphics Memory Controller Hub Gmch Intel 82854 Gmch System ArchitectureGmch System Memory Interface Processor Host InterfaceDDR Sdram Memory Capacity Technology WidthDisplay Features Graphics FeaturesGmch Analog Display Port Gmch Integrated DVO PortsAddress Decode Policies Hub InterfaceIntel 82854 Gmch Interface Clocks Gmch ClockingRatio Bytes MB/sSystem Interrupts Buffer Description Notation DescriptionHost Interface Signal Descriptions Host Interface SignalsHIT# DRDY#HITM# HLOCK#RS20# Response type RS20#DDR Sdram Interface Descriptions DDR Sdram InterfaceSRAS# SCAS#Hub Interface Signals Hub Interface SignalsClocks Dpms Display Power Management Signaling This signal is used onlyDAC Clocking DrefclkInternal Graphics Display Signals Digital Video Output B Dvob Port Signal DescriptionsDigital Video Output B Dvob Port Digital Video Output C Dvoc Port Digital Video Output C Dvoc Port Signal DescriptionsDvob and Dvoc Port Common Signal Descriptions Analog CRT Display Signal DescriptionsAnalog CRT Display Gpio Signal Descriptions General Purpose Input/Output SignalsVoltage References, PLL Power Voltage References, PLL PowerPswing HlrcompHlvref VcchlConceptual Overview of the Platform Configuration Structure Device Number AssignmentGmch Function Bus #0, Device# Nomenclature for Access Attributes Nomenclature for Access AttributesStandard PCI Bus Configuration Mechanism Routing Configuration AccessesPCI Bus #0 Configuration Mechanism Default Value upon Reset Primary PCI and Downstream Configuration MechanismRegister Definitions Reserved BitsI/O Mapped Registers Configaddress Configuration Address RegisterReserved Bit DescriptionsConfiguration Data Register Configdata Configuration Data RegisterVGA I/O Mapped Register List VGA I/O Mapped RegistersIndex Data Registers Name Function Read @ Write @Gmch Configuration Space Device #0, Function#0 Register Name Default Value AccessEnd Attbase VID Vendor Identification Register Did Device Identification RegisterBit Descriptions 150 = Serr message is not generated by the Gmch for Device #0 Pcicmd PCI Command RegisterPCI Status Register Subc Sub Class Code Register RID Register IdentificationBCC Base Class Code Register HDR Header Type RegisterSvid Subsystem Vendor Identification Register Capptr Capabilities Pointer Register SID Subsystem Identification RegisterCapability ID Capid Capabilities Identification Register Device #0GMC Gmch Miscellaneous Control Register Device #0 Rrbar Access Enable-R/WMDA Present MDAP-R/W VGAReserved Device #2 Function #1 Enable/Disable GGC Gmch Graphics Control Register Device #0Bit Dafc Device and Function Control Register Device #0 Fdhc Fixed Dram Hold Control Register Device #0Bit Description 17 PAM60 Programmable Attribute Map Register Device #0 Attribute Bit AssignmentBits 7 Bits 6 Bits 5 Bits 4 Description Reserved PAM Registers DOS Application Area 00000h-9FFFh PAM Registers and Associated System Memory SegmentsVideo Buffer Area A0000h-BFFFFh Expansion Area C0000h-DFFFFhExtended System Bios Area E0000h-EFFFFh System Bios Area F0000h-FFFFFhSmram System Management RAM Control Register Device #0 Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Bit Description Reserved Smicmd SMI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error Scicmd SCI Error Command Register Device #0SCI on Single-bit ECC Error SCI on Gmch Thermal Sensor TripReserved FSB Data Bus Power Management Control Reserved On Die Termination ODT Gating DisableC2 state Gmch FSB Interface Power Management Control Shic Secondary Host Interface Control Register Device #0HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DDR Write Recovery time tWR DDR Internal Write to Read Command delay tWTRDRT Dram Timing Register Device #0 Examples of usageBack To Back Read-Read commands spacing DDR, different Rows Encoding CK between RD and WR commandsEncoding CK between RD and RD commands Refresh Cycle Time tRFCActivate to Precharge delay tRAS, MAX Activate to Precharge delay tRAS, MINReserved CAS# Latency tCL CS# Signal Drive Control PCEn Page Close Enable TC Timer Control PDEn23Dynamic Memory Interface Power Management Rcven DLL shutdown disablePower State S1/S3 Refresh Control Ddim DDR Sdram Data Integrity Mode DRC Dram Controller Mode Register Device #0001 000010 011For Double Data Rate DTC Dram Throttling Control Register Device #0 Wttc DDR Sdram Throttle Mode Tmode2724 High Priority Stream Throttling Enable Thermal Power Throttle Control fields EnableHpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpll VCO Change Sequence Initiate Bit Hpllcc Hpll Clock Control Register Device #0HPLLCC20 Straps Read GFX CoreDVO Port CRT Port RateRegs Register NameDid Device Identification Register Device #2 VID Vendor Identification Register Device #2Pcicmd PCI Command Register Device #2 RID Revision Identification Register Device #2 Pcists PCI Status Register Device #2CC Class Code Register Device #2 MLT Master Latency Timer Register Device #2CLS Cache Line Size Register Device #2 Base Class Code Basec 03=Display controllerPrefetchable Memory-RO Enable prefetching Bit Description Master Latency Timer Count Value ROHDR Header Type Register Device #2 Gmadr Graphics Memory Range Address Register Device #2Iobar I/O Base Address Register Device #2 Mmadr Memory Mapped Range Address Register Device #2Prefetchable Memory-RO Prevents prefetching Memory / IO Space-RORomadr Video Bios ROM Base Address Registers Device #2 Svid Subsystem Vendor Identification Register Device #2SID Subsystem Identification Register Device #2 Intrline Interrupt Line Register Device #2 Intrpin Interrupt Pin Register Device #2Mingnt Minimum Grant Register Device #2 Pmcap Power Management Capabilities Register Device #2 Auxiliary Power Source Hardwired toMaxlat Maximum Latency Register Device #2 Bits10 Power State Pmcs Power Management Control/Status Register Device #2Simplified View of System Address Map System Memory Address RangesDetailed View of System Address Map DOS Compatibility AreaDOS Area 000000h-09FFFFh System Memory Segments and Their AttributesLegacy VGA Ranges 0A0000h-0BFFFFh Compatible Smram Address Range 0A0000h-0BFFFFhSystem Bios Area 0F0000h-0FFFFFh Extended System Bios Area 0E0000h-0EFFFFhExtended System Memory Area Monochrome Display Adapter MDA Range 0B0000h 0B7FFFhPre-allocated System Memory 1 15 MB-16 MB WindowPre-allocated System Memory Attributes CommentsHseg Extended Smram Address Range Hseg and TsegTseg Dynamic Video Memory Technology DvmtPCI Memory Address Range Top of Main System Memory to 4 GB High Bios Area FFE00000h -FFFFFFFFhSystem Management Mode SMM Memory Range SMM Space RestrictionsSMM Space Definition System Memory Shadowing 5 I/O Address SpaceSMM Space Transaction Handling PCI I/O Address Mapping Gmch Decode Rules and Cross-Bridge Address MappingHub Interface Decode Rules Hub Interface Accesses to Gmch that Cross Device BoundariesCycles Initiated Using PCI Protocol Accesses to Gmch that Cross Device BoundariesInterface Decode Rules Dynamic Bus Inversion Host Interface OverviewSystem Bus Interrupt Delivery Relation of DBI Bits to Data BitsConfiguration Mechanism for DDR DIMMs System Memory Organization and ConfigurationSystem Memory Interface Upstream Interrupt MessagesSystem Memory Register Programming DDR Sdram Performance DescriptionData Bytes on DDR Dimm Used for Programming Dram Registers Byte Function1 3D/2D Instruction Processing Integrated Graphics Overview2 3D Engine Setup EngineViewport Transform and Perspective Divide 2.3 3D Primitives and Data Formats SupportScan Converter Backface CullingTexture Engine Perspective Correct Texture SupportTexture Chromakey Anti-AliasingTexture Map Filtering Multiple Texture Composition Raster EngineCubic Environment Mapping Bump MappingCombining Intrinsic and Specular Color Components Texture Map BlendingColor Shading Modes Color DitheringAlpha Blending Color Buffer Formats Destination AlphaDepth Buffer Stencil Buffer 4 2D EngineProjective Textures 4.1 256-Bit Pattern Fill and BLT EngineDual Display Usage Model Native Graphic Mode only Hardware Cursor Plane Native Graphic Mode onlyPlanes and Engines Alpha Stretch BLTOverlay Plane Dynamic Bob and Weave Color ControlMPEG-2 Decoding Video FunctionalityHardware Motion Compensation Sub-picture SupportPipe a Timing Generator Unit Internal Graphic Display InterfaceArib Support 1.2 H, V timing signals for active and blank timingHSYNC/VSYNC Field Timing ParametersBlend Function Interlaced Video Field displayInterlace support for Plane a graphics Arib 960 X 540 support DVO Control Data Bits Interlace support for Video Overlay WindowTiming Register Switching Analog Display Port Characteristics Integrated RamdacDDC Display Data Channel 146 D15343-003 Power and Thermal Management General Description of Acpi States General Description of Supported CPU StatesInternal Thermal Sensor OverviewHysteresis Operation Usage External Thermal Sensor InputStrapping Configuration Strapping Signals and ConfigurationPin Name Strap Description Configuration Type Buffer Type Intel 82854 Gmch Straps for Frequency/CPU Configuration GST20FSB Freq DDR Freq Gfx Freq Core Vcc Ballout and Package Information VCC/VSS Voltage Groups Voltage Levels and Ball Out for Voltage GroupsName Voltage Level Ball out Ballout Table Row Column Signal Name156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Top ViewIntel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View