Intel D15343-003 manual DDR Sdram Interface Descriptions, Sras#, Scas#, Swe#

Signal Description

3.2DDR SDRAM Interface

Table 6.	DDR SDRAM Interface Descriptions
	Signal Name	Type	Description
	SCS[3:0]#	O	Chip Select: These pins select the particular DDR SDRAM
		SSTL_2	components during the active state.
			NOTE: There is one SCS# per DDR-SDRAM Physical DDR DIMM
			device row. These signals can be toggled on every rising System
			Memory Clock edge (SCMDCLK).
	SMA[12:0]	O	Multiplexed Memory Address: These signals are used to provide the
		SSTL_2	multiplexed row and column address to the DDR SDRAM.
	SBA[1:0]	O	Bank Select (Memory Bank Address): These signals define which
		SSTL_2	banks are selected within each DDR SDRAM row. The SMA and SBA
			signals combine to address every possible location within a DDR
			SDRAM device.
	SRAS#	O	DDR Row Address Strobe: SRAS# may be heavily loaded and
		SSTL_2	requires tw0 DDR SDRAM clock cycles for setup time to the DDR
			SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define the
			system memory commands.
	SCAS#	O	DDR Column Address Strobe: SCAS# may be heavily loaded and
		SSTL_2	requires two clock cycles for setup time to the DDR SDRAMs. Used
			with SRAS# and SWE# (along with SCS#) to define the system memory
			commands.
	SWE#	O	Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
		SSTL_2	define the DDR SDRAM commands. SWE# is asserted during writes to
			DDR SDRAM. SWE# may be heavily loaded and requires two clock
			cycles for setup time to the DDR SDRAMs.
	SDQ[63:0]	I/O	Data Lines: These signals are used to interface to the DDR SDRAM
		SSTL_2	data bus.
		I/O	Data Strobes: Data strobes are used for capturing data. During writes,
	SDQS[8:0]	SSTL_2	SDQS is centered on data. During reads, SDQS is edge aligned with
			data. The following list matches the data strobe with the data bytes.
			There is an associated data strobe (DQS) for each data signal (DQ) and
			check bit (CB) group.
			SDQS[7] -> SDQ[63:56]
			SDQS[6] -> SDQ[55:48]
			SDQS[5] -> SDQ[47:40]
			SDQS[4] -> SDQ[39:32]
			SDQS[3] -> SDQ[31:24]
			SDQS[2] -> SDQ[23:16]
			SDQS[1] -> SDQ[15:8]
			SDQS[0] -> SDQ[7:0]
	SCKE[3:0]	O	Clock Enable: These pins are used to signal a self-refresh or power
		SSTL_2	down command to the DDR SDRAM array when entering system
			suspend. SCKE is also used to dynamically power down inactive DDR
			SDRAM rows. There is one SCKE per DDR SDRAM row. These
			signals can be toggled on every rising SCK edge.

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