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Intel D15343-003 manual Dafc Device and Function Control Register Device #0, Bit Description

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.8.15DAFC – Device and Function Control Register (Device #0)

Address Offset:	54-55h
Default Value:	0000h
Access:	Read/Write
Size:	16 bits

This 16-bit register controls the visibility of devices and functions within the GMCH to configuration software.

Bit	Description

15:8	Reserved

7	Device #2 Disable:
	1: Disabled.
	0: Enabled.

6:3	Reserved

2	Device #0 Function #3 Disable:
	1: Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges.
	0: Enable Function #3 within Device #0.

1	Reserved

0	Device #0 Function #1 Disable:
	1: Disable Function #1 within Device #0.
	0: Enable Function #1 within Device #0.

4.8.16FDHC – Fixed DRAM Hold Control Register (Device #0)

Address Offset:	58h
Default Value:	00h
Access:	Read/Write
Size:	8 bits

This 8-bit register controls a single fixed DDR SDRAM hole: 15-16 MB.

Bit	Description

7Hole Enable (HEN): This field enables a memory hole in DDR SDRAM space. Host cycles matching an enabled hole are passed onto ICH4-M through Hub interface. The GMCH will ignore Hub interface cycles matching an enabled hole.

NOTE: A selected hole is not re-mapped.

0:None

1:15 MB–16 MB (1MBs)

6:0

Reserved

60	D15343-003

Image 60

Intel D15343-003 Dafc Device and Function Control Register Device #0, Fdhc Fixed Dram Hold Control Register Device #0

Contents

Datasheet Intel 82854 Graphics Memory Controller Hub GmchD15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Revision History Date Revision DescriptionIntel 82854 Graphics Memory Controller Hub Gmch Overview Processor/Host Bus SupportMemory System System Interrupts Video Stream DecoderVideo Overlay Internal Graphics Features DisplayIntel 82854 Graphics Memory Controller Hub Gmch Graphic Power Management Power ManagementHub Interface to ICH4-M Intel 854 Chipset system block diagram Native Graphic mode PackageTerminology Terms and DescriptionsTerm Description ICH4-M Reference Documents Reference DocumentsDocument Location Intel 82854 Graphics Memory Controller Hub Gmch System Architecture Intel 82854 GmchProcessor Host Interface Gmch System Memory InterfaceDDR Sdram Memory Capacity Technology WidthGraphics Features Display FeaturesGmch Analog Display Port Gmch Integrated DVO PortsHub Interface Address Decode PoliciesGmch Clocking Intel 82854 Gmch Interface ClocksRatio Bytes MB/sSystem Interrupts Notation Description Buffer DescriptionHost Interface Signals Host Interface Signal DescriptionsDRDY# HIT#HITM# HLOCK#RS20# RS20# Response typeDDR Sdram Interface DDR Sdram Interface DescriptionsSRAS# SCAS#Hub Interface Signals Hub Interface SignalsClocks Display Power Management Signaling This signal is used only DpmsDAC Clocking DrefclkInternal Graphics Display Signals Digital Video Output B Dvob Port Signal DescriptionsDigital Video Output B Dvob Port Digital Video Output C Dvoc Port Signal Descriptions Digital Video Output C Dvoc PortDvob and Dvoc Port Common Signal Descriptions Analog CRT Display Signal DescriptionsAnalog CRT Display General Purpose Input/Output Signals Gpio Signal DescriptionsVoltage References, PLL Power Voltage References, PLL PowerHlrcomp PswingHlvref VcchlConceptual Overview of the Platform Configuration Structure Device Number AssignmentGmch Function Bus #0, Device# Nomenclature for Access Attributes Nomenclature for Access AttributesStandard PCI Bus Configuration Mechanism Routing Configuration AccessesPCI Bus #0 Configuration Mechanism Primary PCI and Downstream Configuration Mechanism Default Value upon ResetRegister Definitions Reserved BitsConfigaddress Configuration Address Register I/O Mapped RegistersBit Descriptions ReservedConfigdata Configuration Data Register Configuration Data RegisterVGA I/O Mapped Registers VGA I/O Mapped Register ListIndex Data Registers Name Function Read @ Write @Gmch Configuration Space Device #0, Function#0 Register Name Default Value AccessEnd Attbase VID Vendor Identification Register Did Device Identification RegisterBit Descriptions 150 Pcicmd PCI Command Register = Serr message is not generated by the Gmch for Device #0PCI Status Register RID Register Identification Subc Sub Class Code RegisterBCC Base Class Code Register HDR Header Type RegisterSvid Subsystem Vendor Identification Register SID Subsystem Identification Register Capptr Capabilities Pointer RegisterCapid Capabilities Identification Register Device #0 Capability IDRrbar Access Enable-R/W GMC Gmch Miscellaneous Control Register Device #0MDA Present MDAP-R/W VGAReserved Device #2 Function #1 Enable/Disable GGC Gmch Graphics Control Register Device #0Bit Dafc Device and Function Control Register Device #0 Fdhc Fixed Dram Hold Control Register Device #0Bit Description 17 PAM60 Programmable Attribute Map Register Device #0 Attribute Bit AssignmentBits 7 Bits 6 Bits 5 Bits 4 Description Reserved PAM Registers PAM Registers and Associated System Memory Segments DOS Application Area 00000h-9FFFhVideo Buffer Area A0000h-BFFFFh Expansion Area C0000h-DFFFFhExtended System Bios Area E0000h-EFFFFh System Bios Area F0000h-FFFFFhSmram System Management RAM Control Register Device #0 Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Smicmd SMI Error Command Register Device #0 Bit Description ReservedScicmd SCI Error Command Register Device #0 Reserved SCI on Multiple-bit ECC ErrorSCI on Single-bit ECC Error SCI on Gmch Thermal Sensor TripReserved On Die Termination ODT Gating Disable Reserved FSB Data Bus Power Management ControlC2 state Gmch FSB Interface Power Management Control Shic Secondary Host Interface Control Register Device #0HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DDR Internal Write to Read Command delay tWTR DDR Write Recovery time tWRDRT Dram Timing Register Device #0 Examples of usageEncoding CK between RD and WR commands Back To Back Read-Read commands spacing DDR, different RowsEncoding CK between RD and RD commands Refresh Cycle Time tRFCActivate to Precharge delay tRAS, MAX Activate to Precharge delay tRAS, MINReserved CAS# Latency tCL PCEn Page Close Enable TC Timer Control PDEn23 CS# Signal Drive ControlDynamic Memory Interface Power Management Rcven DLL shutdown disablePower State S1/S3 Refresh Control DRC Dram Controller Mode Register Device #0 Ddim DDR Sdram Data Integrity Mode000 001010 011For Double Data Rate DTC Dram Throttling Control Register Device #0 DDR Sdram Throttle Mode Tmode Wttc2724 Thermal Power Throttle Control fields Enable High Priority Stream Throttling EnableHpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpllcc Hpll Clock Control Register Device #0 Hpll VCO Change Sequence Initiate BitStraps Read GFX Core HPLLCC20DVO Port CRT Port RateRegister Name RegsVID Vendor Identification Register Device #2 Did Device Identification Register Device #2Pcicmd PCI Command Register Device #2 Pcists PCI Status Register Device #2 RID Revision Identification Register Device #2MLT Master Latency Timer Register Device #2 CC Class Code Register Device #2CLS Cache Line Size Register Device #2 Base Class Code Basec 03=Display controllerBit Description Master Latency Timer Count Value RO Prefetchable Memory-RO Enable prefetchingHDR Header Type Register Device #2 Gmadr Graphics Memory Range Address Register Device #2Mmadr Memory Mapped Range Address Register Device #2 Iobar I/O Base Address Register Device #2Prefetchable Memory-RO Prevents prefetching Memory / IO Space-RORomadr Video Bios ROM Base Address Registers Device #2 Svid Subsystem Vendor Identification Register Device #2SID Subsystem Identification Register Device #2 Intrline Interrupt Line Register Device #2 Intrpin Interrupt Pin Register Device #2Mingnt Minimum Grant Register Device #2 Pmcap Power Management Capabilities Register Device #2 Auxiliary Power Source Hardwired toMaxlat Maximum Latency Register Device #2 Pmcs Power Management Control/Status Register Device #2 Bits10 Power StateSystem Memory Address Ranges Simplified View of System Address MapDOS Compatibility Area Detailed View of System Address MapSystem Memory Segments and Their Attributes DOS Area 000000h-09FFFFhLegacy VGA Ranges 0A0000h-0BFFFFh Compatible Smram Address Range 0A0000h-0BFFFFhExtended System Bios Area 0E0000h-0EFFFFh System Bios Area 0F0000h-0FFFFFhExtended System Memory Area Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh1 15 MB-16 MB Window Pre-allocated System MemoryPre-allocated System Memory Attributes CommentsExtended Smram Address Range Hseg and Tseg HsegTseg Dynamic Video Memory Technology DvmtHigh Bios Area FFE00000h -FFFFFFFFh PCI Memory Address Range Top of Main System Memory to 4 GBSystem Management Mode SMM Memory Range SMM Space RestrictionsSMM Space Definition System Memory Shadowing 5 I/O Address SpaceSMM Space Transaction Handling Gmch Decode Rules and Cross-Bridge Address Mapping PCI I/O Address MappingHub Interface Accesses to Gmch that Cross Device Boundaries Hub Interface Decode RulesCycles Initiated Using PCI Protocol Accesses to Gmch that Cross Device BoundariesInterface Decode Rules Host Interface Overview Dynamic Bus InversionSystem Bus Interrupt Delivery Relation of DBI Bits to Data BitsSystem Memory Organization and Configuration Configuration Mechanism for DDR DIMMsSystem Memory Interface Upstream Interrupt MessagesDDR Sdram Performance Description System Memory Register ProgrammingData Bytes on DDR Dimm Used for Programming Dram Registers Byte FunctionIntegrated Graphics Overview 1 3D/2D Instruction ProcessingSetup Engine 2 3D EngineViewport Transform and Perspective Divide 2.3 3D Primitives and Data Formats SupportBackface Culling Scan ConverterTexture Engine Perspective Correct Texture SupportTexture Chromakey Anti-AliasingTexture Map Filtering Raster Engine Multiple Texture CompositionCubic Environment Mapping Bump MappingTexture Map Blending Combining Intrinsic and Specular Color ComponentsColor Shading Modes Color DitheringAlpha Blending Color Buffer Formats Destination AlphaDepth Buffer 4 2D Engine Stencil BufferProjective Textures 4.1 256-Bit Pattern Fill and BLT EngineHardware Cursor Plane Native Graphic Mode only Dual Display Usage Model Native Graphic Mode onlyPlanes and Engines Alpha Stretch BLTOverlay Plane Color Control Dynamic Bob and WeaveVideo Functionality MPEG-2 DecodingHardware Motion Compensation Sub-picture SupportInternal Graphic Display Interface Pipe a Timing Generator Unit1.2 H, V timing signals for active and blank timing Arib SupportParameters HSYNC/VSYNC Field TimingBlend Function Interlaced Video Field displayInterlace support for Plane a graphics Arib 960 X 540 support Interlace support for Video Overlay Window DVO Control Data BitsTiming Register Switching Analog Display Port Characteristics Integrated RamdacDDC Display Data Channel 146 D15343-003 Power and Thermal Management General Description of Supported CPU States General Description of Acpi StatesInternal Thermal Sensor OverviewHysteresis Operation External Thermal Sensor Input UsageStrapping Configuration Strapping Signals and ConfigurationPin Name Strap Description Configuration Type Buffer Type Intel 82854 Gmch Straps for Frequency/CPU Configuration GST20FSB Freq DDR Freq Gfx Freq Core Vcc Ballout and Package Information VCC/VSS Voltage Groups Voltage Levels and Ball Out for Voltage GroupsName Voltage Level Ball out Row Column Signal Name Ballout Table156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Package Mechanical InformationIntel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View