Pcicmd PCI Command Register | Intel D15343-003 guide

Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.9.3PCICMD – PCI Command Register

Address Offset:	04-05h
Default Value:	0006h
Access:	Read Only, Read/Write
Size:	16 bits

Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not implemented.

Bit	Descriptions

15:10	Reserved

9	Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-
	to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to
	0. Writes to this bit position have no affect.

8	SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH
	and this bit is hardwired to 0. Writes to this bit position have no effect.

7	Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the
	GMCH, and this bit is hardwired to 0. Writes to this bit position have no effect.

6	Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to
	0. Writes to this bit position have no effect.

5	VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is
	hardwired to a 0. Writes to this bit position have no effect.

4	Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and
	Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no
	effect.

3	Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0.
	Writes to this bit position have no effect.

2	Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is
	hardwired to a 1. Writes to this bit position have no effect.

1	Memory Access Enable (MAE): The GMCH always allows access to main system memory. This
	bit is not implemented and is hardwired to 1. Writes to this bit position have no effect.

0	I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0.
	Writes to this bit position have no effect.

74	D15343-003

Image 74

Intel D15343-003 manual Pcicmd PCI Command Register

Contents

Datasheet Intel 82854 Graphics Memory Controller Hub Gmch D15343-003 Contents Intel 82854 Graphics Memory Controller Hub Gmch 10.9 127 Figures 152 Revision History Date Revision Description Intel 82854 Graphics Memory Controller Hub Gmch Memory System OverviewProcessor/Host Bus Support Video Overlay System InterruptsVideo Stream Decoder Internal Graphics Features Display Intel 82854 Graphics Memory Controller Hub Gmch Hub Interface to ICH4-M Graphic Power ManagementPower Management Intel 854 Chipset system block diagram Native Graphic mode Package Term Description TerminologyTerms and Descriptions ICH4-M Document Location Reference DocumentsReference Documents Intel 82854 Graphics Memory Controller Hub Gmch System Architecture Intel 82854 Gmch DDR Sdram Memory Capacity Processor Host InterfaceGmch System Memory Interface Technology Width Gmch Analog Display Port Graphics FeaturesDisplay Features Gmch Integrated DVO Ports Hub Interface Address Decode Policies Ratio Gmch ClockingIntel 82854 Gmch Interface Clocks Bytes MB/s System Interrupts Notation Description Buffer Description Host Interface Signals Host Interface Signal Descriptions HITM# DRDY#HIT# HLOCK# RS20# RS20# Response type SRAS# DDR Sdram InterfaceDDR Sdram Interface Descriptions SCAS# Hub Interface Signals Hub Interface Signals Clocks DAC Clocking Display Power Management Signaling This signal is used onlyDpms Drefclk Digital Video Output B Dvob Port Internal Graphics Display SignalsDigital Video Output B Dvob Port Signal Descriptions Digital Video Output C Dvoc Port Signal Descriptions Digital Video Output C Dvoc Port Analog CRT Display Dvob and Dvoc Port Common Signal DescriptionsAnalog CRT Display Signal Descriptions General Purpose Input/Output Signals Gpio Signal Descriptions Voltage References, PLL Power Voltage References, PLL Power Hlvref HlrcompPswing Vcchl Gmch Function Bus #0, Device# Conceptual Overview of the Platform Configuration StructureDevice Number Assignment Nomenclature for Access Attributes Nomenclature for Access Attributes PCI Bus #0 Configuration Mechanism Standard PCI Bus Configuration MechanismRouting Configuration Accesses Register Definitions Primary PCI and Downstream Configuration MechanismDefault Value upon Reset Reserved Bits Configaddress Configuration Address Register I/O Mapped Registers Bit Descriptions Reserved Configdata Configuration Data Register Configuration Data Register Index Data Registers VGA I/O Mapped RegistersVGA I/O Mapped Register List Name Function Read @ Write @ End Gmch Configuration Space Device #0, Function#0Register Name Default Value Access Attbase Bit Descriptions 150 VID Vendor Identification RegisterDid Device Identification Register Pcicmd PCI Command Register = Serr message is not generated by the Gmch for Device #0 PCI Status Register RID Register Identification Subc Sub Class Code Register Svid Subsystem Vendor Identification Register BCC Base Class Code RegisterHDR Header Type Register SID Subsystem Identification Register Capptr Capabilities Pointer Register Capid Capabilities Identification Register Device #0 Capability ID MDA Present MDAP-R/W Rrbar Access Enable-R/WGMC Gmch Miscellaneous Control Register Device #0 VGA Bit Reserved Device #2 Function #1 Enable/DisableGGC Gmch Graphics Control Register Device #0 Bit Description Dafc Device and Function Control Register Device #0Fdhc Fixed Dram Hold Control Register Device #0 Bits 7 Bits 6 Bits 5 Bits 4 Description Reserved 17 PAM60 Programmable Attribute Map Register Device #0Attribute Bit Assignment PAM Registers Video Buffer Area A0000h-BFFFFh PAM Registers and Associated System Memory SegmentsDOS Application Area 00000h-9FFFh Expansion Area C0000h-DFFFFh Smram System Management RAM Control Register Device #0 Extended System Bios Area E0000h-EFFFFhSystem Bios Area F0000h-FFFFFh Esmramc Extended System Management RAM Control Device #0 Errsts Error Status Register Device #0 Errcmd Error Command Register Device #0 Smicmd SMI Error Command Register Device #0 Bit Description Reserved SCI on Single-bit ECC Error Scicmd SCI Error Command Register Device #0Reserved SCI on Multiple-bit ECC Error SCI on Gmch Thermal Sensor Trip C2 state Gmch FSB Interface Power Management Control Reserved On Die Termination ODT Gating DisableReserved FSB Data Bus Power Management Control Shic Secondary Host Interface Control Register Device #0 HEM Host Error Control, Status, and Observation Device #0 DRB VID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register Device. Reads and Writes to this location have no effect DRB Dram Row 03 Boundary Register Device #0 DRA Dram Row Attribute Register Device #0 DRT Dram Timing Register Device #0 DDR Internal Write to Read Command delay tWTRDDR Write Recovery time tWR Examples of usage Encoding CK between RD and RD commands Encoding CK between RD and WR commandsBack To Back Read-Read commands spacing DDR, different Rows Refresh Cycle Time tRFC Reserved CAS# Latency tCL Activate to Precharge delay tRAS, MAXActivate to Precharge delay tRAS, MIN Dynamic Memory Interface Power Management PCEn Page Close Enable TC Timer Control PDEn23CS# Signal Drive Control Rcven DLL shutdown disable Power State S1/S3 Refresh Control DRC Dram Controller Mode Register Device #0 Ddim DDR Sdram Data Integrity Mode 010 000001 011 For Double Data Rate DTC Dram Throttling Control Register Device #0 DDR Sdram Throttle Mode Tmode Wttc 2724 Thermal Power Throttle Control fields Enable High Priority Stream Throttling Enable Hpllcc Did Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register Subc Sub-Class Code Register ID Subsystem Identification Register Hpllcc Hpll Clock Control Register Device #0 Hpll VCO Change Sequence Initiate Bit DVO Port CRT Port Straps Read GFX CoreHPLLCC20 Rate Register Name Regs VID Vendor Identification Register Device #2 Did Device Identification Register Device #2 Pcicmd PCI Command Register Device #2 Pcists PCI Status Register Device #2 RID Revision Identification Register Device #2 CLS Cache Line Size Register Device #2 MLT Master Latency Timer Register Device #2CC Class Code Register Device #2 Base Class Code Basec 03=Display controller HDR Header Type Register Device #2 Bit Description Master Latency Timer Count Value ROPrefetchable Memory-RO Enable prefetching Gmadr Graphics Memory Range Address Register Device #2 Prefetchable Memory-RO Prevents prefetching Mmadr Memory Mapped Range Address Register Device #2Iobar I/O Base Address Register Device #2 Memory / IO Space-RO SID Subsystem Identification Register Device #2 Romadr Video Bios ROM Base Address Registers Device #2Svid Subsystem Vendor Identification Register Device #2 Mingnt Minimum Grant Register Device #2 Intrline Interrupt Line Register Device #2Intrpin Interrupt Pin Register Device #2 Maxlat Maximum Latency Register Device #2 Pmcap Power Management Capabilities Register Device #2Auxiliary Power Source Hardwired to Pmcs Power Management Control/Status Register Device #2 Bits10 Power State System Memory Address Ranges Simplified View of System Address Map DOS Compatibility Area Detailed View of System Address Map Legacy VGA Ranges 0A0000h-0BFFFFh System Memory Segments and Their AttributesDOS Area 000000h-09FFFFh Compatible Smram Address Range 0A0000h-0BFFFFh Extended System Memory Area Extended System Bios Area 0E0000h-0EFFFFhSystem Bios Area 0F0000h-0FFFFFh Monochrome Display Adapter MDA Range 0B0000h 0B7FFFh Pre-allocated System Memory 1 15 MB-16 MB WindowPre-allocated System Memory Attributes Comments Tseg Extended Smram Address Range Hseg and TsegHseg Dynamic Video Memory Technology Dvmt High Bios Area FFE00000h -FFFFFFFFh PCI Memory Address Range Top of Main System Memory to 4 GB SMM Space Definition System Management Mode SMM Memory RangeSMM Space Restrictions SMM Space Transaction Handling System Memory Shadowing5 I/O Address Space Gmch Decode Rules and Cross-Bridge Address Mapping PCI I/O Address Mapping Hub Interface Accesses to Gmch that Cross Device Boundaries Hub Interface Decode Rules Interface Decode Rules Cycles Initiated Using PCI ProtocolAccesses to Gmch that Cross Device Boundaries System Bus Interrupt Delivery Host Interface OverviewDynamic Bus Inversion Relation of DBI Bits to Data Bits System Memory Interface System Memory Organization and ConfigurationConfiguration Mechanism for DDR DIMMs Upstream Interrupt Messages Data Bytes on DDR Dimm Used for Programming Dram Registers DDR Sdram Performance DescriptionSystem Memory Register Programming Byte Function Integrated Graphics Overview 1 3D/2D Instruction Processing Viewport Transform and Perspective Divide Setup Engine2 3D Engine 2.3 3D Primitives and Data Formats Support Texture Engine Backface CullingScan Converter Perspective Correct Texture Support Texture Map Filtering Texture ChromakeyAnti-Aliasing Cubic Environment Mapping Raster EngineMultiple Texture Composition Bump Mapping Color Shading Modes Texture Map BlendingCombining Intrinsic and Specular Color Components Color Dithering Depth Buffer Alpha BlendingColor Buffer Formats Destination Alpha Projective Textures 4 2D EngineStencil Buffer 4.1 256-Bit Pattern Fill and BLT Engine Planes and Engines Hardware Cursor Plane Native Graphic Mode onlyDual Display Usage Model Native Graphic Mode only Alpha Stretch BLT Overlay Plane Color Control Dynamic Bob and Weave Hardware Motion Compensation Video FunctionalityMPEG-2 Decoding Sub-picture Support Internal Graphic Display Interface Pipe a Timing Generator Unit 1.2 H, V timing signals for active and blank timing Arib Support Parameters HSYNC/VSYNC Field Timing Interlace support for Plane a graphics Blend FunctionInterlaced Video Field display Arib 960 X 540 support Interlace support for Video Overlay Window DVO Control Data Bits Timing Register Switching DDC Display Data Channel Analog Display Port CharacteristicsIntegrated Ramdac 146 D15343-003 Power and Thermal Management General Description of Supported CPU States General Description of Acpi States Hysteresis Operation Internal Thermal SensorOverview External Thermal Sensor Input Usage Pin Name Strap Description Configuration Type Buffer Type Strapping ConfigurationStrapping Signals and Configuration FSB Freq DDR Freq Gfx Freq Core Vcc Intel 82854 Gmch Straps for Frequency/CPU ConfigurationGST20 Ballout and Package Information Name Voltage Level Ball out VCC/VSS Voltage GroupsVoltage Levels and Ball Out for Voltage Groups Row Column Signal Name Ballout Table 156 D15343-003 D15343-003 157 158 D15343-003 D15343-003 159 160 D15343-003 D15343-003 161 162 D15343-003 D15343-003 163 Intel 82854 Gmch Micro-FCBGA Package Dimensions Top View Package Mechanical Information Intel 82854 Gmch Micro-FCBGA Package Dimensions Side View Intel 82854 Gmch Micro-FCBGA Package Dimensions Bottom View