StrongARM Core Software, System Programming Model | Intel IXP1200

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

The StrongARM core shares access to SRAM and DRAM with the microengines, and thus can manage the VC and IP tables. The StrongARM core runs a Developer’s Workbench debug library to connect to Developer’s Workbench running on a remote host to debug and download microcode.

Figure 6. System Programming Model

2.2StrongARM Core Software

In this example implementation, the StrongARM core runs VxWorks, and initializes the hardware; controls the baseboard 82559 PCI Ethernet NIC; runs the IXP1200 Developer's Workbench debug library, and connects it to a remote system host via the PCI Ethernet NIC; runs various startup utilities (including atm_init() to initialize the IP route and VC Lookup tables) and provides those utilities for run-time; and runs an agent to consume exception packets which are not handled by the microengines in the data plane.

In the simulation environment, the IP and VC table management software are emulated with Transactor foreign models - DLLs which are linked into the Transactor. The same source code is compiled into the Transactor foreign models for SIMULATION, and the VxWorks utilities to run on HARDWARE.

14	Application Note

Modified on: 3/20/02,

Image 14

Intel IXP1200 manual StrongARM Core Software, System Programming Model

Contents

IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol Processing Frame and PDU Length vs. IP Packet Length SAR Expected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet Length Execution Environment Software Developer’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model StrongARM Core Software System Programming Model Software Partitioning ATM TX Lookup Tables VC Lookup Data FlowATM to Ethernet Data Flow IP Lookup Table ATM to Ethernet Processing Steps StrongARM Core Initialization Ethernet to ATM Data Flow ATM Receive Microengine Microengine Functional BlocksMicroengine Initialization Structure High Level Algorithm OC-12 Port OC-3 Ports ATM Transmit Microengine ATM Transmit High Level Algorithm IP-Router Microengine Ethernet Receive Microengine Ethernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in Dram CRC-32 Hardware Generation on Transmit Transmit Alignment CRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and Generator CRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Computation Vctablehashed Structure Vctablelinear Structure Primary VC Table VC Table Management API atmutils.c VC Table Entry Cell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache Structure IP Table Function IP Lookup TableVC Cache API IP Table Structure Mtuchange IP Table Management APIRoutetableinit Atmrouteadd Routedelete EnetrouteaddRtentinfo Rthelp Sram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8 ATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdr Sequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call Description Example Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line Analogy Msgqinitregs Msgqhandle ParametersMsgqinitqueue Msgqsend Msgqreceive Ramoption Buffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management Macros Counters Count Counter Base Address Global ParametersUse of the Counter Subsystem Counter Index #define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group Description Portcounterinc Counters.uc CounterresetCounterinc Portcounterinc Algorithm Intotaldiscards Counters.c Countersinit Countersprint Global $transfer Register Name Manager xfer.uc Atmtxcrcbadbd Mutexvectorenter Mutex VectorsMutexvectorinit Mutexvectorexit Projectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... Bytes Related Documents Title Description