Intel IXP1200 Document Conventions, Acronyms & Definitions, 10 11 12 13 14 15 16 ... Bytes

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

10.0Document Conventions

In illustrations of 32-bit registers, or data structures in memory; smaller addresses appear toward the top of the figure, - as they would appear in a memory dump on the screen. Bit positions are numbered from the right to the left.

Figure 37. Illustration of Array of 32-bit Words

bits	3	3	2	2	2	2	2	2	2	2	2	2	1	1	1	1	1	1	1	1	1	1	9	8	7	6	5	4	3	2	1	0
	1	0	9	8	7	6	5	4	3	2	1	0	9	8	7	6	5	4	3	2	1	0
address
				Byte 0								Byte 1								Byte 2								Byte 3
n
address
				Byte 4								Byte 5								Byte 6								Byte 7
n+1
address
				Byte 8								Byte 9								Byte 10								Byte 11
n+2

Bytes are numbered from left to right as shown in the array in Figure 37, as well as in the example byte sequence inFigure 38. Bytes of a word are numbered starting at the most significant byte.

Figure 38. Illustration of Byte Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ... Bytes

Ethernet Dest. Address

Ethernet Source Address

Type

IP... .. IP

11.0Acronyms & Definitions

Figure 39. Definitions

Term	Definition
AAL	ATM Adaptation Layer
AAL5	ATM Adaption Layer 5 (data)
API	Application Programming Interface
ARP (or ATM ARP)	Address Resolution Protocol
ATM	Asynchronous Transfer Mode
BDQ	Buffer Descriptor Queue
CRC	Cyclic Redundancy Check
CS (or AAL5-CS)	Convergence Sub-Layer
DLL	Dynamic Link Library
DWBF	Developer’s Workbench - Integrated Development
	environment for the IXP1240 Network Processor
Fast Port	A port that has its own dedicated status lines
GPR
IP	Internet Protocol
MAC	Media Access Controller

Application Note 57

Modified on: 3/20/02,