Mutex Vectors, Mutexvectorinit, Mutexvectorenter | Intel IXP1200

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

// sram[read, $foo], ordered, ctx_swap

4.10Mutex Vectors

Mutex vectors are an extension to critical sections that allows multiple critical sections to be contained within a single absolute register. (critsect.uc implements critical sections, critsect macros are documented in the IXP1200 Macro Library Reference Manual.) Critsect macros are used to allow only 1 of the 4 threads of a microengine to execute a critical code section at one time. The critsect macros allow the four threads within a microengine to use a semaphore implemented in an absolute register. The semaphore is used to restrict use of a resource shared by the threads in a microengine. The OC-3 Ethernet receiver uses them to prevent multiple threads from enqueuing on the same transmit queue, while allowing them to concurrently enqueue on different transmit queues. The mutex vector subsystem is implemented in mutex_vector.uc.

The following critical section macros are for use within a microengine. Up to 32 critical sections can be implemented with each absolute register. These macros are used where run-time selection between multiple mutexes is necessary. If only one mutex is needed, the macros in critsect.uc are slightly smaller and faster.

4.10.1mutex_vector_init()

Initializes critical sections to enable subsequent mutex_vector_enter() to succeed.

mutex_vector_init(out_abs_reg)

Parameter	Description

out_abs_reg	Absolute register containing the semaphores.

4.10.2mutex_vector_enter()

Enters the specified microengine critical section.

mutex_vector_enter(io_abs_reg, in_bit_number)

	Parameter	Description

	out_abs_reg	Absolute register containing the semaphores.

		bit number of the semaphore
	in_bit_number	0 bits: critical section available
	in_bit_number	1 bits: critical section occupied
		1 bits: critical section occupied
		init: clears all bits

4.10.3mutex_vector_exit()

Exits the specified microengine critical section.

mutex_vector_exit(io_abs_reg, in_bit_number)

Application Note

53

Modified on: 3/20/02,

Image 53

Intel IXP1200 manual Mutex Vectors, Mutexvectorinit, Mutexvectorenter, Mutexvectorexit

Contents

IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol Processing SAR Frame and PDU Length vs. IP Packet Length Frame and PDU Length vs. IP Packet Length Expected Ethernet Transmit Bandwidth Software Execution Environment Developer’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model System Programming Model StrongARM Core Software ATM TX Software Partitioning Lookup Tables VC Lookup Data FlowATM to Ethernet Data Flow ATM to Ethernet Processing Steps IP Lookup Table Ethernet to ATM Data Flow StrongARM Core Initialization Microengine Initialization Microengine Functional BlocksATM Receive Microengine Structure OC-12 Port OC-3 Ports High Level Algorithm ATM Transmit High Level Algorithm ATM Transmit Microengine Ethernet Receive Microengine IP-Router Microengine Ethernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure First Cell of a PDU in Rfifo and in Dram Bytes Big Endian Diagram Transmit Alignment CRC-32 Hardware Generation on Transmit Functional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRC Virtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 Computation Vctablehashed Structure Primary VC Table Vctablelinear Structure VC Table Entry VC Table Management API atmutils.c Cell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache Structure VC Cache API IP Lookup TableIP Table Function IP Table Structure Routetableinit IP Table Management APIMtuchange Atmrouteadd Rtentinfo EnetrouteaddRoutedelete Rthelp 2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data Buffers ATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdr System Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call Description Usage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line Analogy Msgqinitqueue Msgqhandle ParametersMsgqinitregs Msgqsend Ramoption Msgqreceive Feature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management Macros Count Counters Use of the Counter Subsystem Global ParametersCounter Base Address Counter Index Counter Flags Global Counter Enable and Flags#define Statement Description Counter Group Description Portcounterinc Counters.uc CounterresetCounterinc Intotaldiscards Portcounterinc Algorithm Countersprint Counters.c Countersinit Atmtxcrcbadbd Global $transfer Register Name Manager xfer.uc Mutexvectorinit Mutex VectorsMutexvectorenter Mutexvectorexit Projectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... Bytes Title Description Related Documents