IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design
28 Application Note
Modified on: 3/20/02,
The hardware byte aligner operates on the data before the CRC computation hardware. This can be
seen in the transfer to quadword 0 of the TFIFO element with sdram_crc[t_fifo_wr], mask_right
with a byte alignment of 2 and a CRC mask value of 4.
Quadwords 1-5 are transferred with sdram_crc[t_fifo_wr, 5] with the same alignment. For
quadword 6, the processing depends upon whether or not it is the last cell of a PDU:
•If quadword 6 is not the last cell, it is transferred via sdram[t_fifo_wr], mask_left, then the
syndrome is extracted for use when the next cell is sent on this VC.
•If quadword 6 is the last cell, the syndrome is read after quadword 5 is finished, it is inverted
and transferred viat_fifo_wr[] to quadword 6 from the microengine.
In all cases, after the cell is transferred and CRC is done, the first quadword is overwritten by the
microengine to insert the ATM header on the front of the cell. As the TFIFO is addressable only as
quadwords, the write will also update the first four bytes of cell payload (labeled LLC0 in the
example diagram). To preserve these first four payload bytes, the microengine first reads them
from DRAM and combines them with the ATM header before overwriting quadword0.
As with LLC0 in the ATM receiver, this design can be optimized to take advantage of that the
constant LLC0 constitutes the first four bytes of payload on the first cell of a PDU (with the initial
configuration, it is enabled by default):
#define CRC32_TX_LLC0
3.7 CRC-32 Checker and Generator Microengines (Soft-CRC)
The CRC-32 microengine code, "Software CRC", is needed only for IXP1200 configurations.
IXP1240 or IXP1250 designs employ sdram_crc[] hardware instructions to perform the same
calculation more efficiently.
In IXP1200 configurations, there are two microengines dedicated to AAL5 CRC-32 calculations:
•One consumes the ATM Receive data stream and checks the CRC-32 before routing to
Ethernet Transmit packet-queues.
•One consumes the Ethernet Receive data stream and generates CRC-32 before forwarding to
the appropriate ATM Transmit queues.
3.7.1 Functional Differences between Checker and Generator
There are four functional differences between the Checker and Generator:
•DRAM data buffer payload alignment: depends on if it was received from ATM or Ethernet.
•Queues to be consumed.
•Queues to be supplied.
•CRC-32 answer - the checker compares it to the received CRC, while the Generator writes it
into the AAL5 trailer.
The source code is assembled into bi naries optimal for Checking or Gen erating based on the
microengine number assignments from system_config.h.
#define CRC_CHECKER (UENGINE_ID == CRC32_CHECKER_UENGINE)
#define CRC_GENERATOR(UENGINE_ID == CRC32_GENERATOR_UENGINE)