Microengine Functional Blocks, Structure | Intel IXP1200 manual

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

3.Run the IXP1200 Developer’s Workbench debug library, and connects it to a remote system host via the PCI Ethernet NIC to download and debug IXP1240 microcode.

Then, atm_init() is invoked to initialize data structures in memory:

•Buffer Descriptor Free-list.

•CRC-32 Lookup Table.

•IP Lookup Table.

•VC Lookup Table and hash miss free-list.

•IP directed broadcast address hash table.

•Ethernet receive port MAC address hash table.

On hardware, atm_init() resides in the atm_utils.o VxWorks-loadable module running on the StrongARM core. In the simulation environment, atm_init() resides in the atm_util.dll foreign model and is invoked from the Transactor startup script atm_ether_init.ind.

2.6Microengine Initialization

One microengine includes system_init.uc and invokes system_init() at its beginning. system_init() is the central microcode initialization macro. It handles initialization not handled by the StrongARM core, and then sends a signal to thread0 of every microengine, including itself. (system_init() can be invoked from any microengine. ether_tx_threads.uc is used simply because of available microstore space.)

Reset causes every microengine to execute thread0 first, so every microengine begins with thread0 waiting for the inter-thread signal from system_init(). Upon receipt, thread0 is responsible for starting up the microengine in an orderly fashion, e.g. initializing absolute registers and signaling the other threads to start.

3.0Microengine Functional Blocks

3.1ATM Receive Microengine

The ATM Receive microengine is a single microengine dedicated to receive cells from the ATM ports, check CRC-32 while re-assembling them into PDUs, and then forward them to the IP Router microengine. (In the software CRC configuration, an additional microengine is used to handle CRC checking.)

3.1.1Structure

The following identifies the ATM Receive microengine structure for OC-12 and OC-3 ports:

OC-12 Port	OC-3 Ports

Four threads working in parallel on one port.	One thread/port.

20	Application Note

Modified on: 3/20/02,

Image 20

Intel IXP1200 manual Microengine Functional Blocks, Microengine Initialization, ATM Receive Microengine, Structure

Contents

IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol Processing Frame and PDU Length vs. IP Packet Length SAR Expected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet Length Execution Environment Software Developer’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model StrongARM Core Software System Programming Model Software Partitioning ATM TX Lookup Tables VC Lookup Data FlowATM to Ethernet Data Flow IP Lookup Table ATM to Ethernet Processing Steps StrongARM Core Initialization Ethernet to ATM Data Flow Microengine Functional Blocks Microengine InitializationATM Receive Microengine Structure High Level Algorithm OC-12 Port OC-3 Ports ATM Transmit Microengine ATM Transmit High Level Algorithm IP-Router Microengine Ethernet Receive Microengine Ethernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in Dram CRC-32 Hardware Generation on Transmit Transmit Alignment CRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and Generator Software Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 Computation Vctablehashed Structure Vctablelinear Structure Primary VC Table VC Table Management API atmutils.c VC Table Entry Cell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache Structure IP Lookup Table VC Cache APIIP Table Function IP Table Structure IP Table Management API RoutetableinitMtuchange Atmrouteadd Enetrouteadd RtentinfoRoutedelete Rthelp Sram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8 ATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdr Sequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call Description Message Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line Analogy Msgqhandle Parameters MsgqinitqueueMsgqinitregs Msgqsend Msgqreceive Ramoption 1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management Macros Counters Count Global Parameters Use of the Counter SubsystemCounter Base Address Counter Index Global Counter Enable and Flags Counter Flags#define Statement Description Counter Group Description Portcounterinc Counters.uc CounterresetCounterinc Portcounterinc Algorithm Intotaldiscards Counters.c Countersinit Countersprint Global $transfer Register Name Manager xfer.uc Atmtxcrcbadbd Mutex Vectors MutexvectorinitMutexvectorenter Mutexvectorexit Projectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... Bytes Related Documents Title Description