IXP1200 Network Processor Family ATM
1.2.1Supported / Not Implemented Functions
The following identifies the ATM, Ethernet, and StrongARM supported functions, as well as those functions that are not supported.
ATM Support | Ethernet Support | StrongARM Core | NOT Implemented | |
Processing Hooks | ||||
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Up to 8 100Mbps | RFC1812 compliance. | Control Plane processing. | ||
Ethernet ports (full |
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Segmentation and Re- | duplex). | AAL5 Protocol data units | ATM Traffic shaping. | |
| (PDUs) for signaling, |
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assembly (SAR). | Routing from |
| ATM ARP support. | |
ATM Adaptation Layer 5 | Ethernet to ATM | (ILMI, LECS, PNNI, CIP) |
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ports based on IP. | forwarded to the |
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(AAL5 with |
| StrongARM core. |
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IP over ATM LLC/SNAP |
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Encapsulation. |
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Routing from ATM to |
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Ethernet ports based on IP. |
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Unspecified Bit Rate |
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(UBR). |
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Full ATM VC name space. |
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16K Virtual Circuits (VC) |
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simultaneously in use. |
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The majority of RFC1812 router validations are performed in the layer 3 forwarding code running on the microengines, while rare case exception packets are sent to the StrongARM core control plane for validation and processing. No processing code on the StrongARM core is currently implemented. Refer to the document "IXP1200 Network Processor RFC 1812 Compliant Layer 3 Forwarding Example Design Implementation Details" for further information.
This example design can be configured to run in three different hardware/software configurations (see the README.TXT file for further information):
Configuration | Description | |
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One ATM | For use with the IXP1240/1250, which uses hardware CRC capability. | |
100Mbps Ethernet ports | ||
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Four ATM | Similar to the above configuration (requires the IXP1240/50), except that | |
100Mbps Ethernet ports | it uses four | |
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Two ATM | For use with the IXP1200 (which does not have hardware CRC | |
capability). Instead, CRC computation is performed by two microengines | ||
100Mbps Ethernet ports | ||
(thus the reduced data rates). | ||
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1.3Background
1.3.1Ethernet, IP and AAL5 Protocol Processing
Figure 1 identifies how this design processes Ethernet, IP, and AAL5 protocols., Reading from top to bottom, Ethernet packets go through the LLC/SNAP Encapsulation, followed by segmentation into ATM AAL5 cells. Reading from bottom to top, it also shows the reverse process, in which AAL5 cells are reassembled into Ethernet packets.
8 | Application Note |
Modified on: 3/20/02,
